Re: [USRP-users] Burst Transmit/Acquisition on X310 (or other USRP)

Looks like there is suffecient buffering on usrp for timed transmit with a slim (1 gig) interface. Not so for rx though... On Dec 8, 2017 1:05 PM, "John Malsbury" wrote: > I have an urgent need to do a quick finite burst/acquisition app with an > X310.

[USRP-users] Burst Transmit/Acquisition on X310 (or other USRP)

I have an urgent need to do a quick finite burst/acquisition app with an X310. Basically, I'd like to perform a timed transmission of 2e6 complex samples to the radio, and do an aligned acquisition of 2e6 samples from the receiver at exactly the same sample clock cycle. I need to do this from a

[USRP-users] X310 degraded SNR

Note that the CBX lower frequency "limit" is around 1.2GHz while the UBX is quite happy tuning down to 10MHz. There are many powerful ambient signal sources between 10MHz and 1.2GHz. I suspect you are seeing those. Nonlinearity being what it is, I have seen AM broadcast signals appear in the

Re: [USRP-users] RFNoC Out-of-tree block controller setup

Well, per usual, I believe I've figured this out with some more digging... 1. If I run a python program that includes my OOT module, the blocks are registered correctly with the block_ctrl_base_factory, and the initialization call to ettus.device3 will correctly correlate my FPGA CE with the OOT

Re: [USRP-users] UHD 3.10.2.0 | X300 - ERROR_CODE_TIMEOUT with low rates

Hi Kyle, Thank you for the good information. We will be increasing the timeout in the next release of UHD, so the issues should be resolved soon. Regards, Michael On Wed, Nov 15, 2017 at 9:19 AM, Guilbert, Kyle J via USRP-users < usrp-users@lists.ettus.com> wrote: > Greetings, > > I am

Re: [USRP-users] X310 degraded SNR

On 12/08/2017 09:18 AM, Mark Koenig via USRP-users wrote: I am mainly looking at frequencies above 2 GHz, would adjusting the dB_clock_rate be something that may help with the noise floor and help my SNR? For reasons beyond my control, I am currently using UHD rev 003.009.007. I hope this

[USRP-users] RFNoC Out-of-tree block controller setup

Hi All, I'm having trouble getting an OOT RFNoC block controller to register correctly with the rfnoc block factory. The goal here is to create a block controller class that attaches to the FPGA CE. I've traced this operation down to the block_ctrl_base_factory.cpp, which exposes the

Re: [USRP-users] X310 degraded SNR

I am mainly looking at frequencies above 2 GHz, would adjusting the dB_clock_rate be something that may help with the noise floor and help my SNR? For reasons beyond my control, I am currently using UHD rev 003.009.007. I hope this not an issue. Thank you Mark From: Mark Koenig

Re: [USRP-users] Multiple RFNoC blocks instantiated

P.S. Obviously i have compiled 2 instances of the block into the FPGA image, maybe i need to add some unique identification at this point? On 8 December 2017 at 12:42, Mark Luscombe wrote: > Hi, > > I've found that if i add a second instance of the same RFNoC block to a >

[USRP-users] Multiple RFNoC blocks instantiated

Hi, I've found that if i add a second instance of the same RFNoC block to a GRC signal flow it fails to compile, complaining that there are duplicate connections to the first instance of the RFNoC block. This happens with either my own RFNoC blocks or Ettus RFNoC blocks. Am i missing something as