Following up on this, I have an additional question: is there any plan to
expose the DC offset and IQ balance API through device3? Currently it
appears as though the legacy interface can make use of these functions to
manually set IQ balance and DC offset, while device3-based programs (i.e.,
Hi Dan. Such a product is in the works. It was mentioned in Manuel Uhm's
presentation at GRCon 2017-- the USRP E320.
Single board approximately the size of a B210, AD9361, RFNoC-capable with
larger Zynq FPGA than E310 (XC7Z045).
Ettus Research intends to demo the E320 at GRCon 2018, so sign up
What I meant and didn't explain well enough is a potential new Ettus
product would be a Zynq-based B2X0 clone. That would be RFNOC-capable.
On Fri, Jun 29, 2018 at 2:32 PM Ian Buckley via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Er no.
>
> B200 has approximately the same number of
Er no.
B200 has approximately the same number of FPGA logic gates as E310, B210 twice
that amount.
The current design is simply larger than it needs to be because it shares all
it’s code with X300, I could have made it much smaller had there been a good
reason to.
The FPGA was simply
Ian,
It turns out the B210s were not phase aligned (contrary to my earlier
report)- we had not done our measurements correctly. So, need to get the
MCS proof-of-concept working on two B210s i.e. just prove on the scope that
the baseband RX sample clocks are indeed aligned. Currently we call a
I think what would be more useful is a low-end USRP (low price like B200)
that is RFNOC-capable. I guess that might be something like an E310 in a
white case?
On Fri, Jun 29, 2018 at 9:12 AM GhostOp14 via USRP-users <
usrp-users@lists.ettus.com> wrote:
> I second RFNoC for the B series would be
Hi,
I'm trying to add an AXI Uartlite
(https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf)
module to the E310 and will be using two GPIO pins for the serial TX/RX. I've
added the IP to e310.v, and hooked it up to twp GPIO pins and the AXI
On Fri, Jun 29, 2018 at 9:57 AM Jason Matusiak <
ja...@gardettoengineering.com> wrote:
> I missed that, thanks for the heads up. I replaced the
> two chdr_deframer_2clk functions with the old chdr_deframer, but that
> didn't seem to fix things for me. Guess I will have to do a deep dive into
>
I missed that, thanks for the heads up. I replaced the two chdr_deframer_2clk
functions with the old chdr_deframer, but that didn't seem to fix things for
me. Guess I will have to do a deep dive into the block with chipscope and try
to see how things flow. My gut is really telling me it has
I second RFNoC for the B series would be great. They're an incredibly
popular and affordable series and I feel a little left out of the
capabilities of RFNoC due to the Spartan6. Bringing the Artix to the
B-series or supporting the Spartan6 could both be options I'd love to see.
(Just a
To give an uplifting spin to all this:
Now, also, although larger than the one on the B200, the B210's FPGA
isn't really large unoccupied, so the amount of logic that you could
even hypothetically put in there is limited. Why's that uplifiting?
That FPGA was chosen for the board because there's
Dear Brad,
wiggle-ability and subsequent change of properties point to a hardware
defect.
Can you please contact supp...@ettus.com with your device's serial
number, if you have, your NI invoice number, and if possible, a closeup
photo of the soldering or the plug, whatever seems wiggly?
Thanks!
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