Hello all, I'm trying to implement better synchronization for SDR base GSM mobile station (wiki of the project: https://osmocom.org/projects/osmocom-bb-sdr-phy/wiki).
Currently the mobile station computes clock offset and applies correction in software to a fractional resampler, in order to achieve more accurate sample frequency synchronization in relation to a GSM BTS. However doing this in software is still a bit awkward. It would be much simpler (in terms of implementation and in terms of computations) to have the correction applied at the hardware level. For example Lime chip based designs (like LimeSDR or XTRX) have a DAC attached between FPGA and VCTCXO, so it is possible to directly adjust the clock source frequency. I noticed that AD9361 has DACs for controlling stuff and started to think how to connect it to the VCTCXO tune input. Then I looked at the B210 schematic and noticed there actually is a path from one of these DAC outputs to the VCTCXO, but disconnected with use of missing R118 resistor: schmatic: https://imgur.com/a/cgTfJ5G pcb: https://imgur.com/a/NYhYxAb My questions: 1. Is it possible to put a resistor (with some correct resistance) in R118 place and not break AD9361 or ADF4001 or any other chip on B210? 2. If not - do you know what other circuit modifications might be needed? 3. Does anyone have experience with adjusting VCTCXO frequency though AD9361 DAC (this is probably question to B210 designer)? Best Regards, Piotr Krysik _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
