[USRP-users] USB 3.0 PCI express card recommendations?

Hi, I'd like to use a high sample rate with a B210 device but I'm limited by my host computer, as it has only USB 2.0 interfaces. The cheapest solution would be to install a USB 3.0 PCI express card, but I found some old thread (2013) where an user experienced some problems (thread link

Re: [USRP-users] Unexpected (increasing) latency for set_rx_gain

hat could we expect to be the main issues (unwanted effects) if we don't? Regards, Brais. El lun., 4 feb. 2019 a las 20:24, Marcus Müller () escribió: > Hi Brais, > > On Mon, 2019-02-04 at 18:34 +0100, Brais Ares via USRP-users wrote: > > Hello, > > > > I'm trying to implemen

Re: [USRP-users] Regarding rx latencies in B200mini

Ok, I understand. Thank you, Marcus. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Re: [USRP-users] Regarding rx latencies in B200mini

Hi Marcus, > Theoretically, there'll be analog group delays that will add some > harder-to-predict latency, but they'll be much smaller than the > time interval represented by the timestamps. Ok, we can consider those analog delays negligible. Sorry to insist but, do I still need to

Re: [USRP-users] Weird effects setting external clock source in a B200mini

I also happen to have some spare B200 devices around and I can confirm what @Martin stated. Since we are working in a jitter-sensitive critical application and after the tests I've perfomed, I'm inclined to think the minimum jitter scenario occurs when using the internal reference (2 ppm), given

[USRP-users] Regarding rx latencies in B200mini

Hello, I have two questions regarding UHD/B200mini latencies: - We need to timestamp, as accurate as possible, some RF signal received by an antenna. Assuming I've got the device time right, my guess is I can use time_spec_t

[USRP-users] Weird effects setting external clock source in a B200mini

Hello, We've just bought an *AXIOM90 OCXO* [1] (actual configuration: 5 V, ±*50 ppb, +7.7 dBm*) and we are having trouble configuring it as an external clock reference on a B200mini. All we do in code is set the clock source as external: - *usrp->set_clock_source("external");* And loop

Re: [USRP-users] Hello,

Thanks Sam! If I understand correctly the link that you refer to, it is possible to obtain time and phase synchronization with B210s, so the only issue would be to compensate phase offset which could be done by software. Could you elaborate a little bit more? I'm probably missunderstading the

[USRP-users] Hello,

Why is the b210 USRP not recommended for use with octoclock for synchronizing several USRPs according to table 4 in [1]? is it still possible to do it? [1] https://kb.ettus.com/Selecting_an_USRP_Device Regards, Brais. ___ USRP-users mailing list

Re: [USRP-users] E300 JTAG Accesory kit compatibility

Thank you, Robin. We​'ll proceed to buy the Kit then. We'll keep in mind the sidenote, as we'll probably need to buy a couple extra Xilinx USB platforms :). Regards, Brais. ___ USRP-users mailing list USRP-users@lists.ettus.com

Re: [USRP-users] Spikes at beginning and end of transmission

Thank you Marcus once again, crystal clear now. 2018-03-21 16:17 GMT+01:00 Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com>: > On 03/21/2018 03:51 AM, Brais Ares via USRP-users wrote: > > ​Hi, > > I can see a similar spike, a few microseconds long, at th

Re: [USRP-users] B210 - How much input power can its TX chains endure?

7/2018 06:29 PM, Brais Ares via USRP-users wrote: > > Hello, > > We are planning to use a B210 device in a project where there may be high > power interferences. > > What would be the *maximum input power through a B210 RF output* to > prevent damaging the device? > (The AD

[USRP-users] B210 - How much input power can its TX chains endure?

Hello, We are planning to use a B210 device in a project where there may be high power interferences. What would be the *maximum input power through a B210 RF output* to prevent damaging the device? (The AD9361 datasheet indicates an absolute maximum of 2.5 dBm for an RF input, but it does not

Re: [USRP-users] USRP E310 and its DC suppression

RP-users wrote: > > On 02/28/2018 03:32 PM, Brais Ares via USRP-users wrote: > > Hello, > > We are using a E310 device to capture a signal and further process it in > Matlab. We also have a frontend that lift the received signal around 43 dB > before going into the E310. >

[USRP-users] USRP E310 and its DC suppression

Hello, We are using a E310 device to capture a signal and further process it in Matlab. We also have a frontend that lift the received signal around 43 dB before going into the E310. When we use direct RF to baseband conversion we observe a high DC suppression, around 50 dB (see figure here

Re: [USRP-users] Running RFNoC examples on E310

​Nevermind. I forgot to source "set_env". Now I need to enable GSPDO option somehow using pyBOMBS. If I can't get it to work I will open a new thread, so that this one does not get too much deviation. Cheers, ~Brais. ___ USRP-users mailing list

Re: [USRP-users] Running RFNoC examples on E310

Hi, ​I had a minor​ improvement... I used a different prefix when using pybombs: $ pybombs prefix init ~/prefix -R *e3xx-latest-maint* -a e300 (installs UHD_003.009.002-0-unknown version) Instead of: $ pybombs prefix init ~/prefix -R e3xx-rfnoc

Re: [USRP-users] Running RFNoC examples on E310

​Hello, I'm experiencing the same problems as Paul and Ronakraj did.​ It seems the automatic installation using PyBOMBS falls in that error: "RuntimeError: RuntimeError: On node 0/FIFO_0, output port 0 is already connected". Will it be fixed soon or is there any easy workaround? I also tried

Re: [USRP-users] Is it possible to manually configure any filter in AD/FPGA

SW, AD and FPGA filter configuration would be automatically chosen. I just want to override it. Hope this makes sense and there is a way to do it. Regards, Brais. 2017-11-02 20:46 GMT+01:00 Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com>: > On 11/02/2017 02:04 PM, Brais Ares

[USRP-users] Is it possible to manually configure any filter in AD/FPGA

Hello everybody, We've just acquired a B210 USRP and *we'd like to know if it's possible to customize AD filters and FPGA filters* (bandwidth, decimation/interpolation factors, and so on). Among UHD drivers I only found this: - *virtual void uhd::usrp::multi_usrp::set_filter* But I'm not

Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

t; https://kb.ettus.com/Getting_Started_with_RFNoC_Development >>> https://www.youtube.com/watch?v=j-EfyPVpaJ8 >>> >>> If you only want to add a filter or two there is already an FIR block >>> which you could either directly make use of or make hopefully minor &

Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

s://github.com/EttusResearch/fpga/blob/6996ed662e5ae170e60ab8cb6de54c > 362cecf8d2/usrp3/lib/rfnoc/noc_block_fir_filter.v#L141 > > Regards, > Derek > > > On Thu, Sep 21, 2017 at 4:48 PM, Brais Ares via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> He

[USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Hello, We want to add some blocks to HDL design in E310 device. We followed the instructions to build Vivado project and it worked okay. Thing is the built design when opened in Vivado looks this way ... where design sources

Re: [USRP-users] Error when receiving for a long period of time

07:00 AM, Brais Ares via USRP-users wrote: > > Hello everyone, > > [USRP E310] > > We need to capture some 300 Hz signal for a long period of time (up to > 15'), as long as a GPIO is '1'. Minimum configurable bandwith is 286 KHz, > what makes us sample the data at 286 KSPS