Re: [USRP-users] List of filters and where they are located

> > [1] > > > https://form.analog.com/Form_Pages/Catalina/CatalinaDesign.aspx?prodid=AD9361 > > [2] https://github.com/jarn0ld/uhd-filter-tool > > > > On 8/25/20 9:09 PM, David Carsenat via USRP-users wrote: > > > Hi, I am using a B205 and

Re: [USRP-users] List of filters and where they are located

s/Catalina/CatalinaDesign.aspx?prodid=AD9361 > [2] https://github.com/jarn0ld/uhd-filter-tool > > On 8/25/20 9:09 PM, David Carsenat via USRP-users wrote: > > Hi, I am using a B205 and I'd just like to know what are the > > difference filter stages (analog and digital) seen by the s

[USRP-users] List of filters and where they are located

Hi, I am using a B205 and I'd just like to know what are the difference filter stages (analog and digital) seen by the signal (both Tx and Rx), in the AD936x and in the FPGA. Another way to help me, should be to have a description of the filter that I can address with the filter.hpp functions : Can

Re: [USRP-users] C++ thread Priority.

te > data to the filesystem at high rates? No amount of code optimization can > get > >>> around the fact that the disk subsystem is very slow compared to > other parts of the computer, like memory, CPU, etc. > >>> > >>> > >

Re: [USRP-users] AD936x disable DC offset removal

That works fine, but I had to change the uhd version to the last one (3.15). Just for information,That does not work on 3.11. Many thanks David Le dim. 26 juil. 2020 à 21:04, Marcus D. Leech a écrit : > On 07/26/2020 02:59 PM, David Carsenat wrote: > > I have tried that, but I see 2 issues (bu

Re: [USRP-users] AD936x disable DC offset removal

I'll try that. Thanks Le dim. 26 juil. 2020 à 21:04, Marcus D. Leech a écrit : > On 07/26/2020 02:59 PM, David Carsenat wrote: > > I have tried that, but I see 2 issues (but perhaps I'm wrong) : > > - I need 25 Mhz of BW so if I want to push the LO outside, I need to > > have a sample rate of 5

Re: [USRP-users] AD936x disable DC offset removal

I have tried that, but I see 2 issues (but perhaps I'm wrong) : - I need 25 Mhz of BW so if I want to push the LO outside, I need to have a sample rate of 50 MHz --> difficult to have Tx / Rx loopback. - I have tried to set the master clock rate at 60 MHz, the DDC offset at 25 MHz, and a sample rat

Re: [USRP-users] AD936x disable DC offset removal

. 26 juil. 2020 à 20:29, Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> a écrit : > On 07/26/2020 02:25 PM, David Carsenat via USRP-users wrote: > > Hello, could someone help me where one can find the UHD Cpp file where > > the DC offset correction of AD936x i

[USRP-users] AD936x disable DC offset removal

Hello, could someone help me where one can find the UHD Cpp file where the DC offset correction of AD936x is enabled ? I need to make a Rx --> Tx loop which is independent of the center frequency of the Rx signal. Thanks a lot David ___ USRP-users mail

Re: [USRP-users] C++ thread Priority.

at high rates? No amount of code optimization can > get > >>> around the fact that the disk subsystem is very slow compared to > other parts of the computer, like memory, CPU, etc. > >>> > >>> > >>> Le mer. 22 juil. 2020 à 19:12, Marcus

Re: [USRP-users] C++ thread Priority.

t; get > around the fact that the disk subsystem is very slow compared to other > parts of the computer, like memory, CPU, etc. > > > Le mer. 22 juil. 2020 à 19:12, Marcus D. Leech via USRP-users < > usrp-users@lists.ettus.com> a écrit : > >> On 07/22/2020 12:56 PM

Re: [USRP-users] C++ thread Priority.

Ok thanks. The code is really simple and i don't think it can be optimized. Is there other linux OS i can try ? Thanks again. Le mer. 22 juil. 2020 à 19:12, Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> a écrit : > On 07/22/2020 12:56 PM, David Carsenat via US

[USRP-users] C++ thread Priority.

Hello, I have made a c++ code which sends samples in the main function and receives samples in a thread launched in this main function. I have read that we can set the real time priority with the set_thread_priority function. I have tried to call this function (with parameters (1,true) inside the m

Re: [USRP-users] b205 RX -> TX loopback

OK thanks. So you confirm the link between UHD sample rate and AD93xx sample rate ? David Le ven. 26 juin 2020 à 00:23, Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> a écrit : > On 06/25/2020 03:04 PM, David Carsenat via USRP-users wrote: > > Hello. > > We

[USRP-users] b205 RX -> TX loopback

Hello. We are trying to make a simple RX on TX loopback by changing the FPGA image. We get it by adding a wire between the DDC output and DUC input, but we are still limited by the sample rate we specify via UHD. We have specified the analog bandwidth at 56 MHz, and the master clock rate at 60 MHz