Hi everyone
I want to build my custom rfnoc image in vivado , and based on some tutorial
did this with running uhd_image_builder.py .But after sometime I got the below
error :
Could not read script '../usrp3/tools/scripts/viv_generate_hls_ip.tcl'
Does anyone know about this?
wrote:
> Yes, I have just been following the guide on the getting started with
> RFNoC page.
>
>
>
> Best Regards,
>
>
>
> Jerrid
>
>
>
> *From:* Brian Padalino
> *Sent:* Thursday, January 2, 2020 8:52 AM
> *To:* Jerrid Plymale
> *Cc:* usrp-users@lis
Felix, thanks for the catch. That looks like a problem I may have
introduced by accident a few months ago. This PR should fix it, hopefully:
https://github.com/EttusResearch/fpga/pull/47/files
Note I expect this would get merged into master and potentially not
backported to whatever version of
Hi Brian,
thank you for the answer, with your help I was able to successfully build
an Image! One last question: Do I need to worry about all those critical
warnings that popped up during the build? Seems like a lot to me.
Example:
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning:
On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi EJ,
>
> thank you for your answer! To make my error more traceable, I created a
> new OOT Module and added the default gain block from rfnoc getting
> started.
>
> I also took your advice and
Hi EJ,
thank you for your answer! To make my error more traceable, I created a
new OOT Module and added the default gain block from rfnoc getting
started.
I also took your advice and looked at the uhd_image_builder.py script. I
noticed very strange behaviour, because my print statements
Hello Cherif and Brian,
I did find the clock signal re-definitions you were talking about in
*rfnoc_ce_auto_inst_x310.v*, and I did notice that the file is generated by the
*uhd_image_builder.py file*, so I looked in the *uhd_image_builder.py* file to
find the code that generates
Hello again,
has no one an idea? I have still not managed to get it working..
I would take any advice!
Best regards,
Felix
> Hello together,
>
> recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install
> of Kubuntu 18.04 LTS. I followed the instructions from
>
On Fri, Jan 3, 2020 at 1:41 PM Cherif Diouf wrote:
> I have this version UHD 3.15.0.git-84-g164d76dc
>
> but the lines are there whenever you use the ./uhd_image_builder.py
> scripts.
>
Ah, I see it now:
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC
MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi Jerrid,
Some hints, for info, I am working with th
On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Jerrid,
>
>
>
> Some hints, for info, I am working with the X310 device, but you can
> take the big picture.
>
>
> I previously met such issues, those were related to signal re-definitions.
>
>
Hi Jerrid,
Some hints, for info, I am working with the X310 device, but you can take the
big picture.
I previously met such issues, those were related to signal re-definitions.
The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the
ce_clk/ce_rst signals by assigning to
Yes, I have just been following the guide on the getting started with RFNoC
page.
Best Regards,
Jerrid
From: Brian Padalino
Sent: Thursday, January 2, 2020 8:52 AM
To: Jerrid Plymale
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC
On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale
wrote:
> I am trying to generate a custom RFNoC FPGA Image using this version of
> UHD.
>
OK. So you've checked out fde2a94eb7231af859653db8caaf777ae2b66199 and
you're trying to build a regular image with Vivado 2018.3. Correct?
Brian
>
I am trying to generate a custom RFNoC FPGA Image using this version of UHD.
Best Regards,
Jerrid
From: Brian Padalino
Sent: Thursday, January 2, 2020 8:44 AM
To: Jerrid Plymale
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC
MDRV
On Thu, Jan 2, 2020 at 11:42 AM Jerrid Plymale
wrote:
> Hello Brian,
>
>
>
> I have installed UHD 3.15.0.0-124-geb448043
>
And this is what you're trying to build?
Brian
>
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Hello Brian,
I have installed UHD 3.15.0.0-124-geb448043
Best Regards,
Jerrid
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On Thu, Jan 2, 2020 at 11:24 AM Jerrid Plymale via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello Marcus,
>
> So I tried cleaning the uhd-fpga folder as you suggested, however I ended
> up getting the same errors and the image still failed to build. I have
> attached the build log again
Hello Jerrid,
huh, a cursory glance tells me this is in the generated IP cores, i.e.
not even in UHD code itself.
I've not encountered that before; maybe there's a half-built IP core
still present in the source tree? You can get that really pristine by
cd uhd-fpga; git clean -xdf
Best regards,
Hello all,
So I have been attempting to build an X310 HG FPGA image following the steps in
the getting started guide for RFNoC for a while now, and I have been getting
the following error:
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC MDRV-1] Multiple Driver Nets:
Hello together,
recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install
of Kubuntu 18.04 LTS. I followed the instructions from
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
and used the Pybombs install.
(I ran into a lot of problems there and had to install a lot
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