On 07/18/2017 02:41 PM, Estrada Lupianez, Jenniffer Marie via USRP-users
wrote:
> Can anyone point to any documentation or give some insight on how the
> E310 FPGA Verilog code design is laid out? I am not familiar with
> Verilog, and just extrapolating from what I understand from VHDL. What
> is t
Hi,
Can anyone point to any documentation or give some insight on how the E310 FPGA
Verilog code design is laid out? I am not familiar with Verilog, and just
extrapolating from what I understand from VHDL. What is the top level module?
The e310.v file? What is the structure? I cannot find any
