Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

Sure, glad to help! Most of magic variables come from the Makefile workflow in uhd-fpga (suggest doing some greps in both uhd-fpga/usrp3/tools/make and uhd-fpga/usrp3/top). The OOT_DIR is a magic variable that's passed to the OOT directory, and it lets the Makefiles resolve relative pathing

Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

Hey EJ, On Tue, Feb 27, 2018 at 6:27 AM, EJ Kreinar wrote: > Hi Brian, > > There's a supported method to include OOT repos that can build and include > xilinx IP (or basically any other IP that you need, including HLS. I've yet > to try it with sysgen blocks, but that would

Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

Hi Brian, There's a supported method to include OOT repos that can build and include xilinx IP (or basically any other IP that you need, including HLS. I've yet to try it with sysgen blocks, but that would probably work too). Basically you can use uhd_image_builder.py or uhd_image_builder_gui.py

[USRP-users] RFNoC FPGA OOT Xilinx IP Addition

Hi, I'm trying to add a piece of Xilinx IP using an .xci file, similar to how the normal flow for the FPGA build goes, but I want to keep it associated with my OOT source, and not change the main FPGA repository. I haven't found any instructions on how to do this, so I figure I'd ask here. Is