Building the X310 FPGA does require a Xilinx Vivado license. It is not one
of the FPGAs for which the free version of the tool works.
You can find instructions for building the FPGA in the user manual:
https://files.ettus.com/manual/md_usrp3_build_instructions.html
Thanks,
Wade
On Fri, Nov 20,
Hi Wade,
Increasing the size of the relevant buffers does sound interesting.
Unfortunately I'm not really familiar with the workflow for building
the FPGA bitstream. I'd be interested in trying it if you could point
me towards up-to-date documentation on doing it, so long as there
wouldn't be a
Hi Dustin,
Based on your other post of the dsp_tune not appearing to have worked, it
seems likely that this is indeed the case and all of your dsp_tune commands
are getting backed up in the FIFO since they are never executed. Does this
seem plausible? This of course doesn't explain why the
On Wed, 2020-11-18 at 19:12 -0600, Wade Fife wrote:
> Dustin,
>
> It sounds like the software thinks the control port FIFO is filling
> up. Are you issuing a lot of timed commands, maybe far into the
> future? I wonder if issuing commands faster than they are being
> executed could cause the FIFO
Dustin,
It sounds like the software thinks the control port FIFO is filling up. Are
you issuing a lot of timed commands, maybe far into the future? I wonder if
issuing commands faster than they are being executed could cause the FIFO
on the FPGA to fill up with commands.
You could try increasing
Hi usrp-users,
terminate called after throwing an instance of 'uhd::op_timeout'
what(): RfnocError: OpTimeout: Control operation timed out waiting
for space in command buffer
I've been getting the error above occasionally, usually after hours of
operation. I've got a few questions about it:
*
