Hello, I am trying to synthesize a custom IP core generated by HLS to generate a RFNoC custom block, but when I run ./uhd_image_builder.py I get the following error:
*--Using the following blocks to generate image: * myFir * despFreq * ddc * fftAdding CE instantiation file for 'X310_RFNOC_HG'changing temporarily working directory to /home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/tools/scripts/../../top/x300Setting up a 64-bit FPGA build environment for the USRP-X3x0...- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)Environment successfully initialized.make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 "make[1]: se entra en el directorio '/home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/top/x300'BUILDER: Checking tools...* GNU bash, versión 4.3.48(1)-release (x86_64-pc-linux-gnu)* Python 2.7.12* Vivado v2017.4 (64-bit)Using parser configuration from: /home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/top/x300/dev_config.json[00:00:00] Executing command: vivado -mode batch -source /home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/top/x300/build_x300.tcl -log build.log -journal x300.jouCRITICAL WARNING: [filemgmt 20-1440] File '/home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v' already exists in the project as a part of sub-design file '/home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'. Explicitly adding the file outside the scope of the sub-design can lead to unintended behaviors and is not recommended.ERROR: [Common 17-107] Cannot change read-only property 'generate_synth_checkpoint'.[00:00:41] Current task: Initialization +++ Current Phase: Starting[00:00:41] Current task: Initialization +++ Current Phase: Finished[00:00:41] Process terminated. Status: Failure========================================================Warnings: 0Critical Warnings: 1Errors: 1Makefile.x300.inc:111: fallo en las instrucciones para el objetivo 'bin'make[1]: *** [bin] Error 1make[1]: se sale del directorio '/home/usrp_2018/rfnoc/src/uhd-fpga/usrp3/top/x300'Makefile:119: fallo en las instrucciones para el objetivo 'X310_RFNOC_HG'make: *** [X310_RFNOC_HG] Error 2* If I synthesize an existing IP Core, it runs fine. I am using a X310 board and 2017.4 vivado version. Does anyone know what it means and how can I solve the problem? Regards, Anabel
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