On 07/10/2017 06:52 AM, Mareike Hetzel via USRP-users wrote:
> Martin,
>
> thank you very much for your help!
>
> I would like to do this! Could you please give me some further
> information what exactly I need to do? As I have never done anything
> with FPGAs, I don't know where to start. I have
Martin,
thank you very much for your help!
I would like to do this! Could you please give me some further
information what exactly I need to do? As I have never done anything
with FPGAs, I don't know where to start. I have to modify the FPGA
image? Will there be only the GPIO definition or
Mareike,
the reason for the delays is that your software is polling the GPIO, and
that goes over network. You're adding in network latency, and SW
scheduling latency.
Also, with the DDC, once a packet leaves the computer, it needs to go
through various stages before it reaches the ADC (after the
