BTW. I found that this question has been already asked a long time ago:
https://lists.gnu.org/archive/html/discuss-gnuradio/2010-09/msg00056.html
but it didn't get any answers back then.
Thanks Ian for the full explanation.
2017-11-09 10:15 GMT+01:00 Ian Buckley :
>
> There’s a bit of history
There’s a bit of history there. PHY_CLK was indeed originally connected to the
FPGA.
It wasn’t needed and so the S1 switch was added to that pin instead.
That switch was never used and so the original signal name persists in the
Verilog even though it connects to nothing.
-Ian
> On Nov 5, 2017,
