I did some more searching and I found this github issue with a workaround:
https://github.com/EttusResearch/uhd/issues/103
(begin quote):
I hit the same ddr3_32bit build error on Windows:
[IP_Flow 19-3475] Tcl error in ::ipgui_ddr3_32bit::updateAllModelParams
procedure for IP 'ddr3_32bit'. Loadi
On 01/26/2018 03:49 PM, Martin K via USRP-users wrote:
> I have Cygwin64 setup in Windows 10
> Vivado 15.4.2 installed and licensed.
>
> [...]
> Some web searching shows that other people have had trouble with the mig
> failing - on both Windows and Linux, but obviously it works for you
> guys. I
I have Cygwin64 setup in Windows 10
Vivado 15.4.2 installed and licensed.
source setupenv.sh --vivado-path=/cygdrive/c/Xilinx/Vivado/
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/cygdrive/c/Xilinx/Vivado//2015.4/bin)
- Vivado HLS: Found (/cygdrive/c/Xilinx/Viva
