ts.ettus.com
> *Subject:* Re: [USRP-users] Building RFNoC image with default blocks
> fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
>
>
>
> On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale <
> jerrid.plym...@canyon-us.com> wrote:
>
> I am trying
Hello Cherif and Brian,
I did find the clock signal re-definitions you were talking about in
*rfnoc_ce_auto_inst_x310.v*, and I did notice that the file is generated by the
*uhd_image_builder.py file*, so I looked in the *uhd_image_builder.py* file to
find the code that generates
On Fri, Jan 3, 2020 at 1:41 PM Cherif Diouf wrote:
> I have this version UHD 3.15.0.git-84-g164d76dc
>
> but the lines are there whenever you use the ./uhd_image_builder.py
> scripts.
>
Ah, I see it now:
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC
MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi Jerrid,
Some hints, for info, I am working with th
On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Jerrid,
>
>
>
> Some hints, for info, I am working with the X310 device, but you can
> take the big picture.
>
>
> I previously met such issues, those were related to signal re-definitions.
>
>
Hi Jerrid,
Some hints, for info, I am working with the X310 device, but you can take the
big picture.
I previously met such issues, those were related to signal re-definitions.
The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the
ce_clk/ce_rst signals by assigning to
Yes, I have just been following the guide on the getting started with RFNoC
page.
Best Regards,
Jerrid
From: Brian Padalino
Sent: Thursday, January 2, 2020 8:52 AM
To: Jerrid Plymale
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC
On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale
wrote:
> I am trying to generate a custom RFNoC FPGA Image using this version of
> UHD.
>
OK. So you've checked out fde2a94eb7231af859653db8caaf777ae2b66199 and
you're trying to build a regular image with Vivado 2018.3. Correct?
Brian
>
I am trying to generate a custom RFNoC FPGA Image using this version of UHD.
Best Regards,
Jerrid
From: Brian Padalino
Sent: Thursday, January 2, 2020 8:44 AM
To: Jerrid Plymale
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC
MDRV
On Thu, Jan 2, 2020 at 11:42 AM Jerrid Plymale
wrote:
> Hello Brian,
>
>
>
> I have installed UHD 3.15.0.0-124-geb448043
>
And this is what you're trying to build?
Brian
>
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Hello Brian,
I have installed UHD 3.15.0.0-124-geb448043
Best Regards,
Jerrid
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On Thu, Jan 2, 2020 at 11:24 AM Jerrid Plymale via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello Marcus,
>
> So I tried cleaning the uhd-fpga folder as you suggested, however I ended
> up getting the same errors and the image still failed to build. I have
> attached the build log again
Hello Jerrid,
huh, a cursory glance tells me this is in the generated IP cores, i.e.
not even in UHD code itself.
I've not encountered that before; maybe there's a half-built IP core
still present in the source tree? You can get that really pristine by
cd uhd-fpga; git clean -xdf
Best regards,
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