Hi Users
I am trying to achieve 50MHz BW (25MHz Each Channel) with X310 and TwinRX
using 1G Ethernet. I went through some of the forums regrading this and found
that X310 does not support 8-bit IQ samples as mentioned in below link.
Hi Michael,
The gnuradio git repository does not have a tag for v3.17.14.5, and using
v3.7.13.5 gives me:
-- Python checking for six - python 2 and 3 compatibility library
-- Python checking for six - python 2 and 3 compatibility library - not
found
CMake Error at volk/CMakeLists.txt:98
Dear friends and fans of software-defined radio and free/open-source radio
topics in general,
FOSDEM 2020 (the free and open-source developer's meeting in Brussels,
Europe) will, once again, feature a track on Software Defined Radio, and
any other radio-related topics in the (now known as) *Free
On 10/16/19 10:33 AM, zcao--- via USRP-users wrote:
> Hi,
>
> UHD lib provides a function, get_time_last_pps(), which suppose to provides
> the time stamp for the latest PPS right edge. I am wondering what is the
> source of the time information the above function uses?
>
> Specifically, we
The E310/E312 has a small-ish FPGA that does not have enough resources to
accommodate the overhead associated with 14 RFNoC blocks. You have
discovered empirically that you run out of space above 5 blocks.
On Wed, Oct 16, 2019 at 10:06 AM Jonathan Lockhart via USRP-users <
Greetings Nate,
So been working through your instructions you linked and everything appears
to be good on the software end. It is all cross-compiling and running on
the E312. Unfortunately there appears to be a new issue. So when running
the GUI for building an FGPA bit file, per the
Hi,
UHD lib provides a function, get_time_last_pps(), which suppose to provides the
time stamp for the latest PPS right edge. I am wondering what is the source of
the time information the above function uses?
Specifically, we are aiming at synchronize multiple E310 devices for a TDMA
system.
Arun,
Sorry for the confusion. The X310 uses a commercial grade XC7K410T with a
temperature range of 0-85C.
Sam
On Tue, Oct 15, 2019 at 10:11 PM Arun kumar Verma
wrote:
> Hi Sam
>
> Thanks for the information. My only doubt is about the FPGA. FPGA is
> industrial grade or Commercial grade ?
Hi list,
since I had a few problems with our new N310s I thought it might be
helpful to share my experience so far.
First off, my initial error during `uhd_usrp_probe` (and also when I
tried to run a GR flowgraph) is fixed.
1. I followed Robins advice to install UHD 3.14.1.1 and use the SD card
Hi Nate,
thanks for the hint. I just double checked. The MTU size is set to 1500
on the device for sfp0. I just attached the output of `ip a` for that.
The MTU is set to 1500 on the host as well.
And yes, the .213 is connected to the sfp0 port.
I ran 2 additional tests. I connected my host and
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