Re: [USRP-users] USRP Underruns "UUUUU"
Hi all, Thank you for all the help! I have tested what kyeong Su Shin mentioned, both on windows and Ubuntu. However, the maximum sampling rate I can go in Windows is 4MS/s but for Ubuntu it can go up to 40MS/s with a only 2-3 U’s to be seen. The problem for me now is that I want to use the FMCW source generator that can be found on my Windows GNU Radio Companion, but I cant find it in Ubuntu, so I cant test out my project using Ubuntu. I’ve tried running https://github.com/scivision/piradar/FMCW_usrp.grc on Ubuntu and the maximum sampling rate I can hit is about 8MS/s. What do you mean by parallelize the bottlenecks (listed below), is there something that I can do to the FMCW_usrp.grc for this? I’ve tried pressing H while running top and nothing seems to pop out or show. Thank you in advance! ---Try using simpler filters, and parallelize the bottlenecks within your flow graphs if possible (so as the CPU usage would go up to approx. 100% during the execution). You can run top and press H to see which block is taking the most CPU time (assuming a typical GNU/Linux distro). --- From: Kyeong Su Shin [mailto:kss...@postech.ac.kr] Sent: Friday, 4 May 2018 6:05 PM To: Yeo Jin Kuang Alvin (IA); usrp-users@lists.ettus.com Subject: RE: USRP Underruns "U" Hello Yeo Jin, First, find the maximum effective sampling rate that you can achieve with your computer. Connect a constant source to a USRP sink (for USRP sink underruns), or connect a USRP source to a null sink (for USRP source overruns) and run the flow graph. Try different sampling rates to find the maximum achievable sampling rate for your hardware (max samp rate that gives no underruns or overruns). If the maximum stable sampling rate that you can achieve is still 4MS/s, then you are pretty much out of luck. You can try installing different versions of GNU Radio and UHD (older version/newer version, version with AVX support, etc) and then try again. If that does not help (very likely), then you WILL have to upgrade your computer. In some cases, using a different network card (for network-based USRPs) or USB card (for USB-based USRPs) may improve the achivable rate (when the bottleneck is the link between the USRP and the PC). If that doesn't work either, then you will have to get a faster machine. If you can achieve a higher sampling rate with the simple flow graphs stated above, then the problem is the maximum throughput of your code. You can try optimizing your GNU Radio flow graphs and blocks. Try using simpler filters, and parallelize the bottlenecks within your flow graphs if possible (so as the CPU usage would go up to approx. 100% during the execution). You can run top and press H to see which block is taking the most CPU time (assuming a typical GNU/Linux distro). If you do not need to generate your I-Q data in real time, then generate your data before the execution of the flow graph and simply play back the pre-generated data (with a File Source block). You can also push down some of your DSP logics to the FPGA of the USRPs, if you have licences for the needed software (and if you are okay with HDL). Regards, Kyeong Su Shin ____ 보낸 사람: Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> 대신 USRP-users <usrp-users-boun...@lists.ettus.com<mailto:usrp-users-boun...@lists.ettus.com>> 보낸 날짜: 2018년 5월 4일 금요일 오후 6:29:09 받는 사람: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> 제목: [USRP-users] USRP Underruns "U" Hi all, I am getting underruns and overruns when trying to run the UHD programs, both GNU radio and C++. The maximum my computer can handle is 4MHz sampling rate before seeing “U”. I’ve searched online and most people say, change a new computer into quad core etc. Are there any other ways to solve this problem? I want to hit around 20 MHz, but 30 MHz – 40MHz if possible. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP to Spectrum Analyzer
Hi all, Theoretically, in frequency domain, the spectrum for SQUARE wave should be a SINC and for the spectrum of RAMP wave should be decreasing with every odd harmonics. A question that I want to ask is, will I get to see these frequency spectrum in the Spectrum Analyzer after being transmitted out from the USRP B210? As I have tried to send a Square and a Ramp wave, I don't see any nice expected waveforms. Is it because of the IQ Modulation in the AD9361 of the USRP B210 that causes me not seeing the expected results? Or is it because of some configurations not done properly? Hope to get a reply soon! Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP Underruns "UUUUU"
Hi all, I am getting underruns and overruns when trying to run the UHD programs, both GNU radio and C++. The maximum my computer can handle is 4MHz sampling rate before seeing "U". I've searched online and most people say, change a new computer into quad core etc. Are there any other ways to solve this problem? I want to hit around 20 MHz, but 30 MHz - 40MHz if possible. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] FPGA or Computer?
Hi all, Just a quick question, everything done using the UHD C++ and GNU Radio Companion, is it done in the FPGA or computer itself? I am using USRP B210 and what is the FPGA used for, as I know Gnu Radio is a software-defined-radio framework, and all the blocks execute on the PC host. Thank you in advanced! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] tx_waveforms example for USRP B210
Hi all, I have tried the tx_waveforms example and measured it using a spectrum analyser (SA). However, no matter what input wave-type I chose, I will get the same output seen in the SA. For example, when I chose SINE and a center frequency of 100MHz, I observed spectrums at 100, 300, 500 ,700 ,900, ... Same waveform is observed for all the different wave-type (RAMP, CONST, SQUARE). Why is this so? It's like only the center frequency is being sent. Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] B210 FPGA Code
Hi, Thanks for the reply! If lets say I would like to bypass all these from the GPIF_D to the tx_codec_d and implement my own signal to the tx_codec_d straight, will I get the same output? Output going into DAC is the same as output transmitting out from DAC. Second question is, must the clock rate of the DDS in the FPGA be the same as the master_clock_rate? Thank you in advance! From: Derek Kozel [mailto:derek.ko...@ettus.com] Sent: Thursday, 26 April 2018 6:39 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] B210 FPGA Code Hello Yeo Jin Kuang Alvin, I am not Ettus' expert in the B210 FPGA, but it would be highly unusual if there were arbitrary bit width changes. I believe that the GPIF bus is 16 bits of I and Q in parallel. The FX3 GPIF bus definition is included in the source and you can use Cypress's tools to look at the configuration of the bus in addition to the FPGA source code. There is considerable DSP implemented in the FPGA, including the decimation, interpolation, and frequency shifting operations. At minimum you would have to make changes to the UHD driver to remove support for those features if you bypass them. My apologies if I've missed this in another email, but what is your goal with these changes? Regards, Derek On Thu, Apr 26, 2018 at 10:18 AM, Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi everyone! For the FPGA source code written for b210, I noticed that the input to the GPIF_D that is 32 bits, and then in went through some FIFOs up converting to 64 bits and then down to 12 bits output (tx_codec_d). May I know what is the purpose of up converting and then down convert again? Will it affect anything if I remove all these and just connect GPIF_D (32 bits) input and take 12 bits MSB (truncation) and connect directly to tx_codec_d (12 bits) ? Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] B210 FPGA Code
I would leave everything as-is in the USRP *except* for the logic the describes the phase accumulator to the DDS (CORDIC). I would replace this logic with logic that generates the desired Chirp response using the CORDIC. Are you referring to b200_core -> radio_legacy -> duc_chain -> cordic_z24 ? If so, I see constants for 24 bit wide phase ( localparam c00…..c23) , do I have to change the values of these constants to form the desired chirp? Is there any guide or examples on how to use the cordic for this FPGA to form a chirp? I would then stream a constant sample value to the USRP in operation which would set the amplitude of my generated Chirp. By streaming a constant sample value to USRP, do you mean by using the UHD to input constant values? If I wanted to make this slightly more complicated to offer programability of the generated Chirp without rebuilding the FPGA, then I would repurpose the incoming sample stream to drive the programable aspects of my phase accumulator, and hard code the amplitude to a constant value. This way I would avoid having to write any host side software to control custom programming registers in the USRP. Do I still have to use the cordic to generate the chirp? There’s no way I can use the Xilinx DDS Coregen to get this working right? From: Ian Buckley [mailto:ian.buck...@gmail.com] Sent: Thursday, 3 May 2018 4:12 AM To: Yeo Jin Kuang Alvin (IA) Cc: Derek Kozel; usrp-users@lists.ettus.com Subject: Re: [USRP-users] B210 FPGA Code Yeo Jin Kuang Alvin, In reply to your original question the data passing over the GPIF interface is packetized data; It contains sample data and control/status data with protocol overhead. It is 32bits due to the design constraints of the FX3. It is transformed to 64bits in the FPGA for maximum code reuse of the same Ettus FPGA code used in all products. The data passing through tx_codec_d is raw (real time) sample data. In answer to your other questions: You are free to discard all the sample data sent over the GPIF interface from the host *ONCE* it has been de-packetized and turned into a raw sample stream…..this is because UHD running on the host will expect to see ACK style protocol communication with the USRP and this is generated by the logic that produces the raw sample stream form the packet stream. You are free to insert whatever new DSP logic you wish inside the DSP but you *must* produce one complex sample output every DSP clock cycle towards the DAC. For the DDS to function in it’s intended purpose, to provide digital frequency translation of your baseband signal before it is sent to the DAC, then yes, it must run at the master clock rate. Now if I were set the same design problem as you, to produce a H/W generated Chirp from a B210 here’s what I might do to generate the least possible amount of design work for myself. I would leave everything as-is in the USRP *except* for the logic the describes the phase accumulator to the DDS (CORDIC). I would replace this logic with logic that generates the desired Chirp response using the CORDIC. I would then stream a constant sample value to the USRP in operation which would set the amplitude of my generated Chirp. If I wanted to make this slightly more complicated to offer programability of the generated Chirp without rebuilding the FPGA, then I would repurpose the incoming sample stream to drive the programable aspects of my phase accumulator, and hard code the amplitude to a constant value. This way I would avoid having to write any host side software to control custom programming registers in the USRP. YMMV, remember this is a suggestion, custom changes to the FPGA don’t have any support. -Ian On May 2, 2018, at 2:14 AM, Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi, Thanks for the reply! If lets say I would like to bypass all these from the GPIF_D to the tx_codec_d and implement my own signal to the tx_codec_d straight, will I get the same output? Output going into DAC is the same as output transmitting out from DAC. Second question is, must the clock rate of the DDS in the FPGA be the same as the master_clock_rate? Thank you in advance! From: Derek Kozel [mailto:derek.ko...@ettus.com] Sent: Thursday, 26 April 2018 6:39 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] B210 FPGA Code Hello Yeo Jin Kuang Alvin, I am not Ettus' expert in the B210 FPGA, but it would be highly unusual if there were arbitrary bit width changes. I believe that the GPIF bus is 16 bits of I and Q in parallel. The FX3 GPIF bus definition is included in the source and you can use Cypress's tools to look at the configuration of the bus in addition to the FPGA source code. There is considerable DSP implemented in the FPGA, including the decimation, interpolation, and frequency shifting
Re: [USRP-users] UHD C++ Chirp Signal
Hello!
1) I've looked into the tx_bursts.cpp code and noticed there isn't any
"wave-type " option, means I assume we have to generate our own signal out/in
this code. Does it mean that if I were to generate the chirp, I have to use
part of the code in tx_waveforms.cpp and type in the chirp's code into
wavetable.hpp so that I am able to send it to the USRP B210 board.
2) If the chirp I would like to generate is 25 MHz with a BW of 20 MHz,
with a transmission pulse width = 2us. Therefore, chirp rate = BW/Tp = 1 x 10^3
.
I am planning to insert this code into the wavetable.hpp to generate the chirp:
If (wave_type == "CHIRP") {
double f_start = 1500;
double f_end = 3500;
double interval = 0.02;
double delta = 0;
double t = 0;
float PI = 3.142;
for (size_t i = 0; i < wave_table_len; i++) {
double delta = i /
(float)wave_table_len;
double t = interval * delta;
double phase = 2 * PI * t *
(f_start + (f_end - f_start) * delta / 2);
real_wave_table[i] =
std::sin(phase);
}
3) The samples required for the chirp is N = tp/ts, correct me if I'm
wrong. But is the ts or sampling frequency fs, the "- -rate" (outgoing samples
to DAC) ?
4) I'm confused at "master_clock_rate" with the "- -rate", if I were to
generate out the chirp mentioned above. What are the rates I have to set for
this two?
Thanks in advance!
From: Humphries, James R. [mailto:humphrie...@ornl.gov]
Sent: Wednesday, 25 April 2018 9:42 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: RE: UHD C++ Chirp Signal
Hello,
One of the UHD examples is a good place to start. I generated chirp bursts a
little while back using the tx_bursts example as a starting point. Most of what
you need is already there, its just up to you to calculate the samples needed
to generate the chirp and put them into the tx buffer.
https://github.com/EttusResearch/uhd/blob/maint/host/examples/tx_bursts.cpp
I'm happy to help if you have any specific questions on this.
-Trip
From: USRP-users
<usrp-users-boun...@lists.ettus.com<mailto:usrp-users-boun...@lists.ettus.com>>
On Behalf Of Yeo Jin Kuang Alvin (IA) via USRP-users
Sent: Monday, April 23, 2018 10:53 PM
To: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] UHD C++ Chirp Signal
Hi all,
Does anyone know how to create a chirp signal using UHD C++? Are there any code
examples and which files do I need?
Thanks in advance!
___
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[USRP-users] B210 FPGA Code
Hi everyone! For the FPGA source code written for b210, I noticed that the input to the GPIF_D that is 32 bits, and then in went through some FIFOs up converting to 64 bits and then down to 12 bits output (tx_codec_d). May I know what is the purpose of up converting and then down convert again? Will it affect anything if I remove all these and just connect GPIF_D (32 bits) input and take 12 bits MSB (truncation) and connect directly to tx_codec_d (12 bits) ? Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Difference between master_clock_rate and rate in UHD
Hi all, As the title mentioned, what is the difference between master_clock_rate and rate in UHD? Which one is the DAC's sampling rate? I'm using USRP B210. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] B210 FPGA Code
Hello, I want to create a chirp signal starting with a 32 bit. I have created the chirp signal internally in the FPGA from 32 bit and truncate down to 12 bit. I have removed the original connection from GPIF_D to tx_code_d. The input of the 32 bit chirp signal is applied internally and the 12 bit output is then connected to the tx_code_d. I not sure if this works, but I have tried uploading this .bin file to the UHD C++ using command prompt and generated out something and looked something like a chirp signal. But however, when I changed the input of my chirp signal, the bandwidth is always around 35 MHz. For example, my signal suppose to be starting from 15 MHz to 35 MHz, with a BW of 20 MHz. When I enter the value of - - freq = 100, I thought this center frequency is suppose to shift the signal to 115 to 135 MHz centered at 125 MHz. But what I see in the spectrum analyser is centered at 100 MHz, with a bandwidth of about ~ 35MHz. Did I misinterpreted something or somewhere wrongly? Thanks in advance! From: Derek Kozel [derek.ko...@ettus.com] Sent: 26 April 2018 18:39 To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] B210 FPGA Code Hello Yeo Jin Kuang Alvin, I am not Ettus' expert in the B210 FPGA, but it would be highly unusual if there were arbitrary bit width changes. I believe that the GPIF bus is 16 bits of I and Q in parallel. The FX3 GPIF bus definition is included in the source and you can use Cypress's tools to look at the configuration of the bus in addition to the FPGA source code. There is considerable DSP implemented in the FPGA, including the decimation, interpolation, and frequency shifting operations. At minimum you would have to make changes to the UHD driver to remove support for those features if you bypass them. My apologies if I've missed this in another email, but what is your goal with these changes? Regards, Derek On Thu, Apr 26, 2018 at 10:18 AM, Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi everyone! For the FPGA source code written for b210, I noticed that the input to the GPIF_D that is 32 bits, and then in went through some FIFOs up converting to 64 bits and then down to 12 bits output (tx_codec_d). May I know what is the purpose of up converting and then down convert again? Will it affect anything if I remove all these and just connect GPIF_D (32 bits) input and take 12 bits MSB (truncation) and connect directly to tx_codec_d (12 bits) ? Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP B210
Hi everyone, I have tried to program the Spartan 6 FPGA using Xilinx 14.7 to send out a signal and to control the AD9361. However, I couldn't get an output out from the transmitter. Can I just solely on FPGA or must I use the API for the USRP B210? What are the steps and procedures I have to do to configure the board, I just feel that I might miss out some important steps. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] USRP B210
From: Yeo Jin Kuang Alvin (IA) Sent: Friday, 6 April 2018 10:55 AM To: 'Neel Pandeya' Subject: RE: [USRP-users] USRP B210 Hi Neel, I am trying to output a chirp signal by creating a DDS in the FPGA using Xilinx ISE 14.7. The code is done from scratch and created a SPI module in the FPGA to control the AD9361 to output the signal. Set up the constraints file gotten from ettus research in git. This are my usual steps: 1) uhd_usrp_probe - -args=”master_clock_rate=40e6” (I am setting to 40MHz as I am using the codec_main_clk in the AD9361 as my main clock, not sure if this is right but simulation/chipscope seems fine ) 2) Opened Xilinx ISE 14.7 3) Generate .bit file 4) Run on IMPACT using JTAG cable 5) Program the file But I couldn’t get any signal out from the transmitter, there is no software C++ or GNU Radio involve. Just solely on FPGA as I am task to create a chirp signal using FPGA. I might have missed out something, like configuration or concept is not right. Just not sure where and how. Thank you in advance! From: Neel Pandeya [mailto:neel.pand...@ettus.com] Sent: Friday, 6 April 2018 10:34 AM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] USRP B210 Hello Yeo Jin Kuang Alvin: If you're modifying the FPGA, then there will likely be a corresponding modification needed on the host-side, especially for something as significant as starting a transmit stream and/or controlling the AD9361 in some way. We'll need much more detail in order to be able to help further. What changes did you make to the FPGA? What exactly are you trying to do overall? --Neel Pandeya On 5 April 2018 at 18:07, Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi everyone, I have tried to program the Spartan 6 FPGA using Xilinx 14.7 to send out a signal and to control the AD9361. However, I couldn’t get an output out from the transmitter. Can I just solely on FPGA or must I use the API for the USRP B210? What are the steps and procedures I have to do to configure the board, I just feel that I might miss out some important steps. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] USRP B210
Hi, I am allowed to do that, but how am I able to do that using ISE 14.7 together with the USRP B210? Thanks in advance! From: Ian Buckley [i...@ionconcepts.com] Sent: 07 April 2018 03:19 To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] USRP B210 Making a hardware DDS to generate a chirp in the FPGA is easy, extremely so if you reuse the Ettus code that interfaces the B210 to AD3961 with correct timing. What is very hard in what you propose, is controlling the AD9361 from within the FPGA without an external host. There is a *lot* of configuration functionality that needs to be captured. Are the constraints of your project such that you are not allowed to have a host connected to USB? On Apr 5, 2018, at 7:57 PM, Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: From: Yeo Jin Kuang Alvin (IA) Sent: Friday, 6 April 2018 10:55 AM To: 'Neel Pandeya' Subject: RE: [USRP-users] USRP B210 Hi Neel, I am trying to output a chirp signal by creating a DDS in the FPGA using Xilinx ISE 14.7. The code is done from scratch and created a SPI module in the FPGA to control the AD9361 to output the signal. Set up the constraints file gotten from ettus research in git. This are my usual steps: 1) uhd_usrp_probe - -args=”master_clock_rate=40e6” (I am setting to 40MHz as I am using the codec_main_clk in the AD9361 as my main clock, not sure if this is right but simulation/chipscope seems fine ) 2) Opened Xilinx ISE 14.7 3) Generate .bit file 4) Run on IMPACT using JTAG cable 5) Program the file But I couldn’t get any signal out from the transmitter, there is no software C++ or GNU Radio involve. Just solely on FPGA as I am task to create a chirp signal using FPGA. I might have missed out something, like configuration or concept is not right. Just not sure where and how. Thank you in advance! From: Neel Pandeya [mailto:neel.pand...@ettus.com] Sent: Friday, 6 April 2018 10:34 AM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] USRP B210 Hello Yeo Jin Kuang Alvin: If you're modifying the FPGA, then there will likely be a corresponding modification needed on the host-side, especially for something as significant as starting a transmit stream and/or controlling the AD9361 in some way. We'll need much more detail in order to be able to help further. What changes did you make to the FPGA? What exactly are you trying to do overall? --Neel Pandeya On 5 April 2018 at 18:07, Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi everyone, I have tried to program the Spartan 6 FPGA using Xilinx 14.7 to send out a signal and to control the AD9361. However, I couldn’t get an output out from the transmitter. Can I just solely on FPGA or must I use the API for the USRP B210? What are the steps and procedures I have to do to configure the board, I just feel that I might miss out some important steps. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Control AD9361 using External Host (USRP B210)
Hi everyone, I want to control the AD9361 in USRP B210 using external host, how can I do it? What are the steps and procedures I have to do? I am using Xilinx ISE 14.7 and Ubuntu. Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Ettus Code (FPGA) for USRP B210
Am I able to run make in Windows using Cygwin for ISE 14.7? I tried to run make
PROJECT_ONLY=1 , and this is what I get.
$ make PROJECT_ONLY=1
/bin/sh: xtclsh: command not found
ISE Version:
make -f Makefile.b200.inc proj NAME=B200 DEVICE=XC6SLX75 EXTRA_DEFS=" "
make[1]: Entering directory
'/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff
6f1f9ae966edd531dc4b611d7/usrp3/top/b200'
/bin/sh: xtclsh: command not found
/bin/sh: xtclsh: command not found
build-B200//b200.xise
xtclsh
/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff6f1f9ae966edd531dc4b61
1d7/usrp3/top/tcl/ise_helper.tcl ""
/bin/sh: xtclsh: command not found
make[1]: *** [../Makefile.common:52: build-B200//b200.xise] Error 127
make[1]: Leaving directory
'/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff6
f1f9ae966edd531dc4b611d7/usrp3/top/b200'
make: *** [Makefile:73: B200] Error 2
--
I ran source C:/Xilinx/14.7/ISE_DS/settings64.bat and I got this
$ source C:/Xilinx/14.7/ISE_DS/settings64.bat
-bash: @echo: command not found
-bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: syntax error near
unexpected token `('
-bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: `REM Copyright (c)
1995-201' Xilinx, Inc. All rights reserved.
From: Robin Coxe [mailto:robin.c...@ettus.com]
Sent: Monday, 9 April 2018 11:16 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Ettus Code (FPGA) for USRP B210
B200.v is the top level Verilog file. If you inspect this file, you will see
that B200_core.v and B200_io.v are instantiated within it.
All of our FPGA code is freely available-- please take some time to look
through the files in the usrp3/lib directories here:
https://github.com/EttusResearch/fpga/tree/maint/usrp3/lib
-Robin
On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users
<usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know which is
the Top file as I noticed there are 3 different ones. B200.v , B200_core.v ,
B200_io.v. Tried to add the source file to Xilinx ISE 14.7 but there are some
files that I couldn’t find, eg. Gpif_sync, slave_fifo32, uart_timing_fifo etc.
What are the essentials file and where do I find it?
Thanks in advance!
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[USRP-users] USRP B210 FPGA Build
Hi everyone, I tried to build the USRP B210 FPGA for Xilinx ISE 14.7 (Windows) and I got this in my cmd prompt: C:\Users\WORK\Desktop\fpga-maint\usrp3\top\b200>make B210 PROJECT_ONLY=1 "ISE Version: Release 14.7 - xtclsh P.20131013 (nt64)" make -f Makefile.b200.inc proj NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="TARGET_B21 0=1 " make[1]: Entering directory `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/b200' make[1]: *** No rule to make target `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/ b200/C:/Users/WORK/Desktop/fpga-maint/usrp3/lib/fifo/axi_demux4.v', needed by `b uild-B210//b200.xise'. Stop. make[1]: Leaving directory `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/b200' make: *** [B210] Error 2 May I know what's missing? The file axi_demux4.v is located there. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP B210 FPGA Generating signal
Hi all, I am currently using USRP B210 and I would like to generate a chirp signal using DDS in the FPGA, I have uploaded the source code by ettus into ISE 14.7. But I am not sure which input and output pin of the code to use, as I have to control the input for the desired chirp signal. Any help would be nice! Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] AD9361 in USRP B210
Hi all, How do we set up the Ad9361_driver and ad9361 controls in the uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites for this? Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] AD9361 in USRP B210
Hi, I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal out that is generated from the FPGA, however I suppose I have to control the AD9361 to get an output out to transmit unless I am wrong. Thanks in advance! From: Nick Foster [mailto:bistrom...@gmail.com] Sent: Thursday, 12 April 2018 9:39 AM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] AD9361 in USRP B210 What exactly do you want to do? On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi all, How do we set up the Ad9361_driver and ad9361 controls in the uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites for this? Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] AD9361 in USRP B210
Hi, Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD software or they can both run concurrently? Thank you in advance! From: Nick Foster [mailto:bistrom...@gmail.com] Sent: Thursday, 12 April 2018 1:28 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] AD9361 in USRP B210 On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, Sorry I am very new to all these, do you mean that I have to download visual studio to compile all the UHD .cpp and run them for the UHD commands? No, I mean that you can probably just get away with using UHD as-is with a program you write (either in Python or C++) invoking a UHD device and configuring it. There are many examples included in uhd/host/examples. If you are lucky you might even get away with using one of the example programs without modification, but I doubt it. And for the FPGA image you talking about, is it the .bit file that is generated in the IMPACT? Yes. You have a long learning curve ahead of you. It's a good idea at this point to simply install UHD and get started using the B210 with some of the UHD examples to see how it works in practice. Nick Thank you in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 12:04 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 The best option is probably to use existing UHD commands to set the gain, frequency, master clock rate, etc., while modifying the image to generate the transmit signal in the FPGA rather than in the host. Nick On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal out that is generated from the FPGA, however I suppose I have to control the AD9361 to get an output out to transmit unless I am wrong. Thanks in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 9:39 AM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 What exactly do you want to do? On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi all, How do we set up the Ad9361_driver and ad9361 controls in the uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites for this? Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] AD9361 in USRP B210
Thank you! :D From: Nick Foster [mailto:bistrom...@gmail.com] Sent: Thursday, 12 April 2018 1:38 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] AD9361 in USRP B210 They are both necessary and serve completely separate and complementary functions. At this point you are best served by reading the documentation. Nick On Wed, Apr 11, 2018, 10:33 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD software or they can both run concurrently? Thank you in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 1:28 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, Sorry I am very new to all these, do you mean that I have to download visual studio to compile all the UHD .cpp and run them for the UHD commands? No, I mean that you can probably just get away with using UHD as-is with a program you write (either in Python or C++) invoking a UHD device and configuring it. There are many examples included in uhd/host/examples. If you are lucky you might even get away with using one of the example programs without modification, but I doubt it. And for the FPGA image you talking about, is it the .bit file that is generated in the IMPACT? Yes. You have a long learning curve ahead of you. It's a good idea at this point to simply install UHD and get started using the B210 with some of the UHD examples to see how it works in practice. Nick Thank you in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 12:04 PM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 The best option is probably to use existing UHD commands to set the gain, frequency, master clock rate, etc., while modifying the image to generate the transmit signal in the FPGA rather than in the host. Nick On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <yjink...@dso.org.sg<mailto:yjink...@dso.org.sg>> wrote: Hi, I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal out that is generated from the FPGA, however I suppose I have to control the AD9361 to get an output out to transmit unless I am wrong. Thanks in advance! From: Nick Foster [mailto:bistrom...@gmail.com<mailto:bistrom...@gmail.com>] Sent: Thursday, 12 April 2018 9:39 AM To: Yeo Jin Kuang Alvin (IA) Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] AD9361 in USRP B210 What exactly do you want to do? On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi all, How do we set up the Ad9361_driver and ad9361 controls in the uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites for this? Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] UHD Open Source Method
Hi all, I followed the ettus research guide https://kb.ettus.com/Building_and_Installing_the_USRP_Open_Source_Toolchain_(UHD_and_GNU_Radio)_on_Windows and start building the *ALL_Build* file. The error I keep getting is LNK1181 cannot open input file '..\lib\Release\uhd.lib' . I checked the folder and it is empty, may I know how do I get the uhd.lib or what is the problem here that I am facing? I am using boost_1_67_0_b1_rc2 (64 bit and version 14), libusb-1.0.21, UHD_3.10.1.1_release, Python 2.7, Mako and CMake 3.11.0. Windows 10, Visual Studio Community 2015. Is there something I missed out? Help would be appreciated. Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] UHD Open Source
Hi all, I would like to download Open Source UHD because I want to edit some files like the AD9361.cpp files. I am currently using: Cmake 3.11.1 ; Visual Studio Express 2015; Boost_1_67_0; LibUSB-1.0.21; Python 2.7; Mako; UHD_3.10.1.1_release; I followed the steps in https://kb.ettus.com/Building_and_Installing_the_USRP_Open_Source_Toolchain_(UHD_and_GNU_Radio)_on_Windows and this is the results shown in CMake: Configuring the python interpreter... Python interpreter: C:/Python27/python.exe Override with: -DPYTHON_EXECUTABLE= fatal: Not a git repository (or any of the parent directories): .git Could not determine git branch. Probably building from tarball. fatal: Not a git repository (or any of the parent directories): .git Using UHD Images Directory: ON Configuring Boost C++ Libraries... Boost version: 1.67.0 Found the following Boost libraries: chrono date_time filesystem program_options regex system unit_test_framework serialization thread atomic Boost include directories: C:/local/boost_1_67_0_x86 Boost library directories: C:/local/boost_1_67_0_x86/lib32-msvc-14.0 Boost libraries: optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_chrono-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_chrono-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_date_time-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_date_time-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_filesystem-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_filesystem-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_program_options-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_program_options-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_regex-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_regex-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_system-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_system-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_unit_test_framework-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_unit_test_framework-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_serialization-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_serialization-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_thread-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_thread-vc140-mt-gd-x32-1_67.lib;optimized;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_atomic-vc140-mt-x32-1_67.lib;debug;C:/local/boost_1_67_0_x86/lib32-msvc-14.0/boost_atomic-vc140-mt-gd-x32-1_67.lib Python checking for Python version 2.7 or greater Python checking for Python version 2.7 or greater - found Python checking for Mako templates 0.4.2 or greater Python checking for Mako templates 0.4.2 or greater - found Python checking for requests 2.0 or greater Python checking for requests 2.0 or greater - found Configuring LibUHD support... Dependency Boost_FOUND = 1 Dependency HAVE_PYTHON_PLAT_MIN_VERSION = TRUE Dependency HAVE_PYTHON_MODULE_MAKO = TRUE Enabling LibUHD support. Override with -DENABLE_LIBUHD=ON/OFF Configuring LibUHD - C API support... Dependency ENABLE_LIBUHD = ON Enabling LibUHD - C API support. Override with -DENABLE_C_API=ON/OFF Configuring Examples support... Dependency ENABLE_LIBUHD = ON Enabling Examples support. Override with -DENABLE_EXAMPLES=ON/OFF Configuring Utils support... Dependency ENABLE_LIBUHD = ON Enabling Utils support. Override with -DENABLE_UTILS=ON/OFF Configuring Tests support... Dependency ENABLE_LIBUHD = ON Enabling Tests support. Override with -DENABLE_TESTS=ON/OFF Could NOT find PkgConfig (missing: PKG_CONFIG_EXECUTABLE) Could NOT find PkgConfig (missing: PKG_CONFIG_EXECUTABLE) Could NOT find LIBGPS (missing: LIBGPS_LIBRARY LIBGPS_INCLUDE_DIR) Configuring USB support... Dependency ENABLE_LIBUHD = ON Dependency LIBUSB_FOUND = TRUE Enabling USB support. Override with -DENABLE_USB=ON/OFF Configuring GPSD support... Dependency ENABLE_LIBUHD = ON Dependency ENABLE_GPSD = Dependency LIBGPS_FOUND = FALSE Disabling GPSD support. Override with -DENABLE_GPSD=ON/OFF Configuring B100 support... Dependency ENABLE_LIBUHD = ON Dependency ENABLE_USB = ON Enabling B100 support. Override with -DENABLE_B100=ON/OFF Configuring B200 support... Dependency ENABLE_LIBUHD = ON Dependency ENABLE_USB = ON Enabling B200 support. Override with -DENABLE_B200=ON/OFF Configuring E100 support... Dependency ENABLE_LIBUHD = ON Dependency LINUX = Disabling E100 support. Override with -DENABLE_E100=ON/OFF Configuring E300 support... Dependency ENABLE_LIBUHD = ON Disabling E300 support. Override with -DENABLE_E300=ON/OFF
[USRP-users] UHD C++ Chirp Signal
Hi all, Does anyone know how to create a chirp signal using UHD C++? Are there any code examples and which files do I need? Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP B210 API & FPGA
Hi all, I have two questions regarding the USRP B210 configurations using API and FPGA at the same time. 1) USRP FPGA Source Code: I have used the Xilinx DDS Compiler using the Coregen and generated out a chirp signal using 2 phase accumulator followed by a SIN_LUT. However, I don't know where to connect the 12 bits output at the SIN_LUT in the source code. Initially, I planned to connect directly to the tx_codec_d, but I noticed that tx_codec_d is connected to b200_io > b200_core > other modules. Can't seem to find a proper input at the Top module or anywhere that I can connect to. My current plan is to connect straight to tx_codec_d and comment off the connection that was previously connected to tx_codec_d in the source code, not sure if it works? 2) USRP API controlling AD9361: I am planning to control the AD9361 in the USRP B210 using the C++ source code given by ettus, located in uhd-maint/host/lib/usrp/common/. I am planning to build the ad9361_device.cpp & ad9361_ctrl.cpp & ad936x_manager.cpp to control the AD9361 to output my chirp signal generated by the FPGA code. Are the steps sufficient to achieve an output or are there more configurations that needs to be done? Hope someone can clarify my doubts and guide me along! Much appreciated! Thanks in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP: AD9361
Hi all, I need to control the AD9361 in the USRP board and I have the AD93611_ctrl.cpp code. The question is if I can just build the ad9361_ctrl.cpp and run the .exe file to control it in the board (Not sure if it will send to the AD9361 in the board) or must I build a certain top file that is higher 'hierarchy' and then edit the ad9361_ctrl.cpp file, build the top file . So that the board can reads it and if this is so, may I know which file to build so that it also consist of the ad9361.cpp files. Thank you in advance! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
