Thank you Marcus, so I need to rev my UHD version to 003.010.001?
Mark
On 8/19/17, 12:02 PM, "USRP-users on behalf of
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Today's Topics:
1. Re: Building FPGA image (Jason Matusiak)
2. Re: How is Resolution and Type Determined From ADC - Using
Ettus rx_samples_to_file.cpp Example (Marcus D. Leech)
3. Re: x310 with twin rx uhd_usrp probe issue (Marcus M?ller)
----------------------------------------------------------------------
Message: 1
Date: Fri, 18 Aug 2017 12:42:14 -0400
From: Jason Matusiak <ja...@gardettoengineering.com>
To: "Torres Figueroa, Luis Angel"
<luis.torres.figue...@rwth-aachen.de>, "usrp-users@lists.ettus.com"
<usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Building FPGA image
Message-ID:
<f8335acb-e28a-0539-33c4-334982532...@gardettoengineering.com>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
I'm glad you got it working. There are a lot of critical warnings and
things of that ilk that scroll by, but as long as you don't get any
errors and your project meets timing, I wouldn't worry too much about them.
Happy FPGAing.
On 08/18/2017 09:26 AM, Torres Figueroa, Luis Angel wrote:
>
> Hi Jason,
>
> It worked. I downloaded the source files from rfnoc-devel branch in
> the repository again and build it without choosing the option you
> mentioned.
>
> I have still some critical warnings, but the image has been correctly
> generated and I could use it in the URSP. Also, all the timing
> constraints were now met. Thanks for the advice!
>
> ImplementationDesign Initialization
>
> [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC
> file
>
/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc
> will not be read for any cell of this module.
>
> [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file
>
/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc
> will not be read for any cell of this module.
>
> [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC
> file
>
/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc
> will not be read for any cell of this module.
>
> [Common 17-55] 'set_property' expects at least one object.
> ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":293]
>
> [Common 17-55] 'set_property' expects at least one object.
> ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":294]
>
> [Common 17-55] 'set_property' expects at least one object.
> ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":295]
>
> Best,
>
> Luis
>
> *Von: *Jason Matusiak <ja...@gardettoengineering.com>
> *Datum: *Mittwoch, 16. August 2017 um 17:09
> *An: *"Torres Figueroa, Luis Angel"
> <luis.torres.figue...@rwth-aachen.de>, "usrp-users@lists.ettus.com"
> <usrp-users@lists.ettus.com>
> *Betreff: *Re: [USRP-users] Building FPGA image
>
> I've done it many times. When you open it and you do a save-as of the
> project, make sure that you don't check the option box to copy the
> files over, you want to leave them in their current location.
>
> On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote:
>
> Hi folks,
>
> Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design
> into Vivado 2015.4 and created the FPGA image using its graphical
> Interface? I am still unable to do so.
>
> I want to create a standard FPGA image using Vivado GUI.
>
> I have first run the command /?make X310_RFNOC_HG GUI=1?/, saved
> the whole RTS design and reopened it as project mode, and then
> tried to create the bitstream from the GUI itself but it doesn?t work.
>
> I have also tried adding the x300.v file, the constraints and all
> its dependent files into the design, and then done the synthesis,
> implementation and generated the bitstream, but when I loaded it
> onto the USRP I can?t recognize any block using the command
> uhd_usrp_probe. This is the error I get:
>
> [ERROR] [UHD] Exception caught in safe-call.
>
> in virtual ctrl_iface_impl::~ctrl_iface_impl()
>
> at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76
>
> this->peek32(0); -> EnvironmentError: IOError: Block ctrl
> (CE_04_Port_70) no response packet - AssertionError: bool(buff)
>
> in uint64_t ctrl_iface_impl::wait_for_ack(bool)
>
> at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197
>
> Best,
>
> Luis A. Torres
>
>
>
>
> _______________________________________________
>
> USRP-users mailing list
>
> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
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------------------------------
Message: 2
Date: Fri, 18 Aug 2017 13:08:56 -0400
From: "Marcus D. Leech" <mle...@ripnet.com>
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] How is Resolution and Type Determined From
ADC - Using Ettus rx_samples_to_file.cpp Example
Message-ID: <59971f28.2050...@ripnet.com>
Content-Type: text/plain; charset="windows-1252"; Format="flowed"
On 08/18/2017 11:24 AM, Matheou, Konstantin J. (GRC-LCI0)[ZIN
TECHNOLOGIES INC] via USRP-users wrote:
>
> Thanks for any help?
>
> I ran the example file from Ettus called rx_samples_to_file.cpp.
>
> I ran the file and it did extract a binary file that I named.
>
> When I analyzed it in matlab using the function ?read_float_binary.m?,
> I received much Nan?s and zeros with actual data?
>
> When I ran the function ?read_cfloat_binary.m?, I received data that
> makes sense.. but is it the correct way???
>
> I realize the binary file has complex value that is interleaved?.
>
> But when I looked at the code rx_samples_to_file.cpp at the end of it
> as shown below?
>
> //recv to file
>
> if (type == "double") recv_to_file<std::complex<double> >(usrp,
> uhd::io_type_t::COMPLEX_FLOAT64, file, spb);
>
> else if (type == "float") recv_to_file<std::complex<float> >(usrp,
> uhd::io_type_t::COMPLEX_FLOAT32, file, spb);
>
> else if (type == "short") recv_to_file<std::complex<short> >(usrp,
> uhd::io_type_t::COMPLEX_INT16, file, spb);
>
> else throw std::runtime_error("Unknown type " + type);
>
> Where is the type defined? I could not find it in the code? Is it in
> a header file? I could not find that either?
>
Each of the UHD examples support a "--help" option. For
rx_samples_to_file, you get:
[INFO] [UHD] linux; GNU C++ version 4.8.3 20140911 (Red Hat 4.8.3-7);
Boost_105400; UHD_4.0.0.rfnoc-devel-239-g89427e8c
UHD RX samples to file Allowed options:
--help help message
--args arg multi uhd device address args
--file arg (=usrp_samples.dat) name of the file to write binary
samples to
--type arg (=short) sample type: double, float, or short
--nsamps arg (=0) total number of samples to receive
--duration arg (=0) total number of seconds to receive
--time arg (DEPRECATED) will go away soon! Use
--duration
instead
--spb arg (=10000) samples per buffer
--rate arg (=1000000) rate of incoming samples
--freq arg (=0) RF center frequency in Hz
--gain arg gain for the RF chain
--ant arg antenna selection
--subdev arg subdevice specification
--bw arg analog frontend filter bandwidth in Hz
--ref arg (=internal) reference source (internal, external,
mimo)
--wirefmt arg (=sc16) wire format (sc8 or sc16)
--setup arg (=1) seconds of setup time
--progress periodically display short-term bandwidth
--stats show average bandwidth on exit
--sizemap track packet size and display
breakdown on
exit
--null run without writing to file
--continue don't abort on a bad packet
--skip-lo skip checking LO lock status
--int-n tune USRP with integer-N tuning
This application streams data from a single channel of a USRP device to
a file.
You can see the default in parenthesis--which in the case of "--type"
defaults to "short".
> There is this if then tree within the matlab finction?.
>
> It seems that the Int16 was used because ?short? was used in the
> Matlab complex function as shown below?.
>
> if(f < 0)
>
> cv = 0;
>
> else
>
> v = fread (f, count, 'short');
>
> fclose (f);
>
> cv = v(1:2:end)+v(2:2:end)*j;
>
> end
>
> This was the output of the constellation?. Thus, noting was over
> +/-32 in the ineger side. Since this kis a 16 bit representation do
> we have 10 bits fractional resolution? S5.10 ???
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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------------------------------
Message: 3
Date: Fri, 18 Aug 2017 19:13:58 +0200
From: Marcus M?ller <marcus.muel...@ettus.com>
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] x310 with twin rx uhd_usrp probe issue
Message-ID: <efab4da1-3c60-256c-5a76-eb14ad847...@ettus.com>
Content-Type: text/plain; charset="windows-1252"
Hi Mark,
the daughterboard EEPROMs are read and return 0x93 and 0x92 as type, and
that's the type of the rev. B version of TwinRX. Support for that was
added in 3.10.1 !
Best regards,
Marcus
On 08/18/2017 05:49 PM, Mark Koenig via USRP-users wrote:
>
> I am currently running CentOS 7.2, UHD rev 003.010.000, and GNU radio
> version 3.7.11. When I probe the USRP, it doesn?t read the
> daughtercards and provide the correct output for frequency, gain,
> bandwidth, etc. Why would this occur? I believe I have all the
> revisions correct. I have pasted the output I am seeing in the emil
> below.
>
>
>
> Any help is appreciated.
>
>
>
> Thank you
>
>
>
> Mark
>
>
>
> When I perform uhd_find devices, I get the output below.
>
>
>
> linux; GNU C++ version 4.8.5; Boost_105300;
> UHD_003.010.000.git-249-gef57ffcb
>
>
>
> --------------------------------------------------
>
> -- UHD Device 0
>
> --------------------------------------------------
>
> Device Address:
>
> type: x300
>
> addr: 192.168.10.2
>
> fpga: HG
>
> name:
>
> serial: F4717C
>
> product: X310
>
>
>
>
>
> When I perform uhd_usrp probe, I get the output below.
>
>
>
> linux; GNU C++ version 4.8.5; Boost_105300;
> UHD_003.010.000.git-249-gef57ffcb
>
>
>
> -- X300 initialization sequence...
>
> -- Determining maximum frame size... 1472 bytes.
>
> -- Setup basic communication...
>
> -- Loading values from EEPROM...
>
> -- Setup RF frontend clocking...
>
> -- Radio 1x clock:200
>
> -- Detecting internal GPSDO.... Found an internal GPSDO
>
> -- Initialize Radio0 control...
>
> -- Performing register loopback test... pass
>
> -- Initialize Radio1 control...
>
> -- Performing register loopback test... pass
>
> _____________________________________________________
>
> /
>
> | Device: X-Series Device
>
> | _____________________________________________________
>
> | /
>
> | | Mboard: X310
>
> | | revision: 4
>
> | | product: 30410
>
> | | mac-addr0: 00:80:2f:0a:e3:35
>
> | | mac-addr1: 00:80:2f:0a:e3:36
>
> | | gateway: 192.168.10.1
>
> | | ip-addr0: 192.168.10.2
>
> | | subnet0: 255.255.255.0
>
> | | ip-addr1: 192.168.20.2
>
> | | subnet1: 255.255.255.0
>
> | | ip-addr2: 192.168.30.2
>
> | | subnet2: 255.255.255.0
>
> | | ip-addr3: 192.168.40.2
>
> | | subnet3: 255.255.255.0
>
> | | serial: F4717C
>
> | | FW Version: 4.0
>
> | | FPGA Version: 20.0
>
> | |
>
> | | Time sources: internal, external, gpsdo
>
> | | Clock sources: internal, external, gpsdo
>
> | | Sensors: gps_gpgga, gps_gprmc, gps_time, gps_locked,
> gps_servo, ref_locked
>
> | | _____________________________________________________
>
> | | /
>
> | | | RX DSP: 0
>
> | | | Freq range: -100.000 to 100.000 MHz
>
> | | _____________________________________________________
>
> | | /
>
> | | | RX DSP: 1
>
> | | | Freq range: -100.000 to 100.000 MHz
>
> | | _____________________________________________________
>
> | | /
>
> | | | RX Dboard: A
>
> | | | ID: Unknown (0x0093)
>
> | | | Serial: 30F2039
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | RX Frontend: 0
>
> | | | | Name: Unknown (0x0093) - 0
>
> | | | | Antennas:
>
> | | | | Sensors:
>
> | | | | Freq range: 0.000 to 0.000 MHz
>
> | | | | Gain Elements: None
>
> | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
>
> | | | | Connection Type: IQ
>
> | | | | Uses LO offset: No
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | RX Codec: A
>
> | | | | Name: ads62p48
>
> | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
>
> | | _____________________________________________________
>
> | | /
>
> | | | RX Dboard: B
>
> | | | ID: Unknown (0x0093)
>
> | | | Serial: 30F2025
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | RX Frontend: 0
>
> | | | | Name: Unknown (0x0093) - 0
>
> | | | | Antennas:
>
> | | | | Sensors:
>
> | | | | Freq range: 0.000 to 0.000 MHz
>
> | | | | Gain Elements: None
>
> | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
>
> | | | | Connection Type: IQ
>
> | | | | Uses LO offset: No
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | RX Codec: B
>
> | | | | Name: ads62p48
>
> | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
>
> | | _____________________________________________________
>
> | | /
>
> | | | TX DSP: 0
>
> | | | Freq range: -100.000 to 100.000 MHz
>
> | | _____________________________________________________
>
> | | /
>
> | | | TX DSP: 1
>
> | | | Freq range: -100.000 to 100.000 MHz
>
> | | _____________________________________________________
>
> | | /
>
> | | | TX Dboard: A
>
> | | | ID: Unknown (0x0092)
>
> | | | Serial: 30F29BC
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | TX Frontend: 0
>
> | | | | Name: Unknown (0x0092) - 0
>
> | | | | Antennas:
>
> | | | | Sensors:
>
> | | | | Freq range: 0.000 to 0.000 MHz
>
> | | | | Gain Elements: None
>
> | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
>
> | | | | Connection Type: IQ
>
> | | | | Uses LO offset: No
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | TX Codec: A
>
> | | | | Name: ad9146
>
> | | | | Gain Elements: None
>
> | | _____________________________________________________
>
> | | /
>
> | | | TX Dboard: B
>
> | | | ID: Unknown (0x0092)
>
> | | | Serial: 30F2B48
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | TX Frontend: 0
>
> | | | | Name: Unknown (0x0092) - 0
>
> | | | | Antennas:
>
> | | | | Sensors:
>
> | | | | Freq range: 0.000 to 0.000 MHz
>
> | | | | Gain Elements: None
>
> | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
>
> | | | | Connection Type: IQ
>
> | | | | Uses LO offset: No
>
> | | | _____________________________________________________
>
> | | | /
>
> | | | | TX Codec: B
>
> | | | | Name: ad9146
>
> | | | | Gain Elements: None
>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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