>>
>>
>>
>> I ran source C:/Xilinx/14.7/ISE_DS/settings64.bat and I got this
>>
>>
>>
>> $ source C:/Xilinx/14.7/ISE_DS/settings64.bat
>>
>> -bash: @echo: command not found
>>
>> -bash: C:/Xilinx/14.7/
hts reserved.
>
>
>
>
>
> *From:* Robin Coxe [mailto:robin.c...@ettus.com]
> *Sent:* Monday, 9 April 2018 11:16 AM
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] Ettus Code (FPGA) for USRP B210
>
>
>
> B200.v i
Copyright (c)
1995-201' Xilinx, Inc. All rights reserved.
From: Robin Coxe [mailto:robin.c...@ettus.com]
Sent: Monday, 9 April 2018 11:16 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Ettus Code (FPGA) for USRP B210
B200.v is the top level Verilog f
B200.v is the top level Verilog file. If you inspect this file, you will
see that B200_core.v and B200_io.v are instantiated within it.
All of our FPGA code is freely available-- please take some time to look
through the files in the usrp3/lib directories here: https://github.com/
On 04/08/2018 10:59 PM, Yeo Jin Kuang Alvin (IA) via USRP-users wrote:
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know
which is the Top file as I noticed there are 3 different ones. B200.v
, B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE
