On Thu, Sep 19, 2019 at 11:18 AM Felix Greiwe
wrote:
> Hi Brian,
>
> thank you for your help.
>
> I have on question left. You say the crossbar is non blocking. Does that
> mean it can supply multiply RFNoC Blocks with input data at once at its
> full bus_clk speed? Or does it switch between the
Hi Brian,
thank you for your help.
I have on question left. You say the crossbar is non blocking. Does that
mean it can supply multiply RFNoC Blocks with input data at once at its
full bus_clk speed? Or does it switch between the ports so that some
blocks have to wait until its their turn to get
On Thu, Sep 19, 2019 at 9:39 AM Felix Greiwe via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello together,
>
> I have some questions concerning clock speeds and the corresponding data
> rates on a USRP x310 (FPGA). As far as I know, there are two different
> clock speeds on the FPGA, the
