Re: [USRP-users] RFNoC Crossbar and Block data rates
On Thu, Sep 19, 2019 at 11:18 AM Felix Greiwe wrote: > Hi Brian, > > thank you for your help. > > I have on question left. You say the crossbar is non blocking. Does that > mean it can supply multiply RFNoC Blocks with input data at once at its > full bus_clk speed? Or does it switch between the ports so that some > blocks have to wait until its their turn to get data? > AXI is a packetized system, but once a packet is ready, as long as there is a 1:1 relationship between ingress and egress, then things should be full rate across all ports. Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC Crossbar and Block data rates
Hi Brian, thank you for your help. I have on question left. You say the crossbar is non blocking. Does that mean it can supply multiply RFNoC Blocks with input data at once at its full bus_clk speed? Or does it switch between the ports so that some blocks have to wait until its their turn to get data? Best regards, Felix > On Thu, Sep 19, 2019 at 9:39 AM Felix Greiwe via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hello together, >> >> I have some questions concerning clock speeds and the corresponding data >> rates on a USRP x310 (FPGA). As far as I know, there are two different >> clock speeds on the FPGA, the ce_clk=200MHz, and the bus_clk - I did not >> find clock speed for this one. >> > > The ce_clk is 214.286 MHz and is usually associated with a 32-bit AXI > interface. > > The bus_clk is 187.5MHz and is usually associated with a 64-bit AXI > interface. > > If you build an FPGA image, you can find these values in > post_route_timing_summary.rpt that Vivado spits out in your build > directory. > > >> >> Is it true, that the ce_clk drives my rfnoc blocks and thus my in- and >> outgoing data rate of each single block (using sc16 samples) is >> 200MHz*32 >> Bit/10^9 = 6,4 GBit/s? >> > > It can, and usually does - but just slightly higher as noted above. > > >> >> I read, that all the RFNoC Blocks are connected to the crossbar which is >> driven by the bus_clk. First of all: Is this the case? >> If so, how is the crossbar able to handle the in and output data of each >> RFNoC Block at once? How many Bytes can it process with each clock? >> >> Take for example the flowgraph >> >> SignalGenerator ->RFNoC-Gain -> RFNoC-DMAFIFO-> RFNoC-DUC-> RFNoC-Radio >> >> which has already four RFNoC Blocks connected to the crossbar, which in >> my >> head are 25,6 GBit/s data on the crossbar at once which seems way to >> much >> to handle. >> >> I think I really miss a point here and would be grateful for some >> explanation. >> > > The crossbar doesn't block other ports and is more like a packet switch. > Since it's a linear flow, the crossbar doesn't have any issue handling > each > individual path bandwidth. Only when 2 packets have to go to the same > crossbar egress do things become more complicated. > > I hope this makes sense. > > Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC Crossbar and Block data rates
On Thu, Sep 19, 2019 at 9:39 AM Felix Greiwe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello together, > > I have some questions concerning clock speeds and the corresponding data > rates on a USRP x310 (FPGA). As far as I know, there are two different > clock speeds on the FPGA, the ce_clk=200MHz, and the bus_clk - I did not > find clock speed for this one. > The ce_clk is 214.286 MHz and is usually associated with a 32-bit AXI interface. The bus_clk is 187.5MHz and is usually associated with a 64-bit AXI interface. If you build an FPGA image, you can find these values in post_route_timing_summary.rpt that Vivado spits out in your build directory. > > Is it true, that the ce_clk drives my rfnoc blocks and thus my in- and > outgoing data rate of each single block (using sc16 samples) is 200MHz*32 > Bit/10^9 = 6,4 GBit/s? > It can, and usually does - but just slightly higher as noted above. > > I read, that all the RFNoC Blocks are connected to the crossbar which is > driven by the bus_clk. First of all: Is this the case? > If so, how is the crossbar able to handle the in and output data of each > RFNoC Block at once? How many Bytes can it process with each clock? > > Take for example the flowgraph > > SignalGenerator ->RFNoC-Gain -> RFNoC-DMAFIFO-> RFNoC-DUC-> RFNoC-Radio > > which has already four RFNoC Blocks connected to the crossbar, which in my > head are 25,6 GBit/s data on the crossbar at once which seems way to much > to handle. > > I think I really miss a point here and would be grateful for some > explanation. > The crossbar doesn't block other ports and is more like a packet switch. Since it's a linear flow, the crossbar doesn't have any issue handling each individual path bandwidth. Only when 2 packets have to go to the same crossbar egress do things become more complicated. I hope this makes sense. Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
