Hi Jonathon,
Yes I don’t really see how this what about the fifo flop vs fifo would be
causing the issue either so it would make sense if there is something more
complex going on...
I am using chdr framer to generate my command packet headers, which is where it
was causing problems. I haven’t
Hi Jonathon,
I have identified the cause of this problem as being chdr_framer.v. It appears
to not be adhering to the axi_stream protocol and is holding onto packets until
the fifo is full even when o_tready is asserted, causing the described behavior.
The root cause is the switch to
Hey Jonathon,
I had a chance to debug this a little further (On an N300) and have observed
the following behavior:
The command packets are getting through to the radio block but are being
buffered somewhere along the line so that the first command is either not
received or not processed until
Hey Sam,
There have been some changes to noc_shell, maybe they are related to your
issue. If you want to try to debug this on the FPGA, I suggest using
chipscope on the file cmd_pkt_proc.v. That is the state machine that
receives command packets and issues settings bus writes. You should be able
Hi Jonathan,
Just following up on this. I have switched to the UHD 3.13 release + FPGA
version 5.2. This issue still persists.
Is it possible that a change to UHD could be causing this to not work?
If anyone can confirm that they are able to send commands to the radio block
from an rfnoc
Hi Jonathan,
Yes I add my block and the radio block, connect them and tell my block to send
commands to radio block. I have confirmed today that the simulation still works
correctly in Vivado 2017.4 — the settings registers are written as expected, an
rx command is generated in the radio and
How does your testbench work? Do you add the radio core block, send timed
commands to it, and see the outputs toggle?
On Sat, Oct 20, 2018 at 1:05 PM Samuel Prager wrote:
> Hi Jonathon,
>
> Thanks for the response! Yes I’m using ce_clk and ce_rst. Thanks for
> sharing your code — the only real
Hi Jonathon,
Thanks for the response! Yes I’m using ce_clk and ce_rst. Thanks for sharing
your code — the only real difference I see is that you increment the seq_num. I
am leaving it as 12’b0 — could this be causing an issue?
I should also say that In my case, the command packets are being
Hi Sam,
I am using command packets to tune the DDC block's DSP frequency. Are you
using ce_clk and ce_rst for clock and reset? Here is my code if you want to
take a look: https://pastebin.com/1AeHFb0J. Also, it might be worth trying
your code on a release tag like v3.13.0.2 in case master has a
