Hey Carlos,
On Tue, Dec 4, 2018 at 1:16 PM Carlos Alberto Ruiz Naranjo <
carlosruiznara...@gmail.com> wrote:
> Hi Brian,
>
> I have finished the DDC block 1:8 and it works perfectly!! :) :)
>
Congratulations!
>
> Now I am in my final step, a 2:16 DDC block:
> - Channels 0:7 connected to input
Hi Brian,
I have finished the DDC block 1:8 and it works perfectly!! :) :)
Now I am in my final step, a 2:16 DDC block:
- Channels 0:7 connected to input 0.
- Channels 8:15 connected to input 1.
The verilog module works, but I have a problem with the UHD driver. I have
timeout on chan
Ok, I had a problem with *radio_block_port. *I had a signed number... :(
I think now it runs. I will pass to 1:8 DCC and later with 2:16 DDC. I
continue... :)
El lun., 3 dic. 2018 a las 16:09, Carlos Alberto Ruiz Naranjo (<
carlosruiznara...@gmail.com>) escribió:
> Hello Brian,
>
> thanks for
Hello Brian,
thanks for your answer! I have returned today and I am testing your changes.
I am using grc and I have the error:
*thread[thread-per-block[0]: ]: LookupError:
KeyError: [0/Radio_0] sr_write(): No such port: 18446744073709551615*
I assume the error is in the configuration of
Hey Carlos,
The attached patch is what I used applied to 3.13.0.1 I want to say. You
get the idea.
To get the controller, I use get_block_ctrl(uhd::rfnoc::block_id_t(0,
"NAME", 0)) since there is only one instance, for me, in my radio.
When setting up the uhd::device_addr_t, I populate:
Hello Brian,
I have finished the FPGA code. I got a DDC 1:2 but I have problems with
1:8. I think I have your same problems: /
*thread[thread-per-block[0]: ]: LookupError:
KeyError: [0/Radio_0] sr_write(): No such port: 2*
In rfnoc code:
*std::vector >
upstream_radio_nodes =
Ok! Thank you :)
El mié., 28 nov. 2018 a las 16:13, Brian Padalino ()
escribió:
> On Wed, Nov 28, 2018 at 9:43 AM Carlos Alberto Ruiz Naranjo <
> carlosruiznara...@gmail.com> wrote:
>
>> Thank you! I already have enough work to continue :)
>>
>> One last thing. In the split_stream module, did
On Wed, Nov 28, 2018 at 9:43 AM Carlos Alberto Ruiz Naranjo <
carlosruiznara...@gmail.com> wrote:
> Thank you! I already have enough work to continue :)
>
> One last thing. In the split_stream module, did you concat tuser with
> m_axis_data_tuser with m_axis_data_tdata?
>
No tuser at that point.
Hey Carlos,
On Tue, Nov 27, 2018 at 6:18 PM Carlos Alberto Ruiz Naranjo <
carlosruiznara...@gmail.com> wrote:
> Hello Brian,
>
> Thank you very much for answering, I am spending a lot of time on this and
> I do not see the way out.
>
> I am following your advice, I have removed the 3 inputs of
Hello Brian,
Thank you very much for answering, I am spending a lot of time on this and
I do not see the way out.
I am following your advice, I have removed the 3 inputs of FPGA code, but I
am having problems.
I have doubts with:
- str_sink_tvalid and str_sink_tready[line 165]
- str_src_tready
On Mon, Nov 26, 2018 at 12:14 PM Carlos Alberto Ruiz Naranjo via USRP-users
wrote:
> Hello,
>
> I have customized the rfnoc DDC. I have:
>
> - 4 inputs (0,1,2,3).
> - 4 outputs (0,1,2,3).
> - 4 independently tunable DDCs.
> - Input 0 connected to outputs 0,1,2,3.
> - Input 1,2,3 disconnected.
>
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