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Today's Topics:
1. Modify the FPGA in X300 (???)
2. Re: Modify the FPGA in X300 (Marcus M?ller)
3. Re: AGC in E310 via UHD? (Martin Braun)
4. Re: [SPAM] Re: Modify the FPGA in X300 (Marcus M?ller)
5. Re: AGC in E310 via UHD? (Zhongren Cao)
6. Re: AGC in E310 via UHD? (Martin Braun)
7. B205mini-I clock source (Oscar S?nchez)
----------------------------------------------------------------------
Message: 1
Date: Mon, 17 Oct 2016 18:40:53 +0800 (GMT+08:00)
From: ??? <2012301650...@whu.edu.cn>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Modify the FPGA in X300
Message-ID:
<5b04c5d2.1cd6f.157d23ad57b.coremail.2012301650...@whu.edu.cn>
Content-Type: text/plain; charset=GBK
Hi all?
To improve the sampling rate ,I hope to modify the bit of output IQ from
16 bits to 2 bits in x300.The FPGA Manual said that the USRP FPGA build system
requires a UNIX-like environment ,can I do it in windows using Xilinx ISE
14.7?I have the fpga-src code,I plan to modify the code and generate the
.bin,is that right?
------------------------------
Message: 2
Date: Mon, 17 Oct 2016 19:25:03 +0200
From: Marcus M?ller <marcus.muel...@ettus.com>
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Modify the FPGA in X300
Message-ID: <cfe4caf0-443b-3730-63d8-e9a08428a...@ettus.com>
Content-Type: text/plain; charset=UTF-8
Hi!
Sampling happens at the maximum that the DAC interface will do with the
default sampling rate of 200MS/s, and you can send that amount of data
without problem across a 10GE link to your PC. On the PC itself,
handling 2 bit samples will not be very efficient, so you'd want to at
least convert them to 8bit. Can you elaborate what exactly you want to
achieve? 2 bit samples certainly don't sound you can then do a lot of
things with the signal... see "Quantization Noise", which, for a
sinusoidal signal, allows a *maximum* SNR of about (1.76 + 2 * 6) dB =
13.76 dB.
regarding build systems: yes, it *is* possible to build the FPGA image
(which these days needs Xilinx Vivado 2015.4) using Cygwin on Windows,
but: Seriously, installing Vivado takes significantly longer than
installing Linux. Just use Linux, it's less hassle. We do support our
customers in every conceivable way, but to be honest: The amount of
people that have time to work with you on the mailing list, are versed
in our FPGA images, the Xilinx tools AND Windows is pretty limited.
Windows, to many of us, still feels like a "strange" OS.
Best regards,
Marcus
On 17.10.2016 12:40, ??? via USRP-users wrote:
> Hi all?
>
> To improve the sampling rate ,I hope to modify the bit of output IQ
> from 16 bits to 2 bits in x300.The FPGA Manual said that the USRP FPGA build
> system requires a UNIX-like environment ,can I do it in windows using Xilinx
> ISE 14.7?I have the fpga-src code,I plan to modify the code and generate the
> .bin,is that right?
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
Message: 3
Date: Mon, 17 Oct 2016 10:49:08 -0700
From: Martin Braun <martin.br...@ettus.com>
To: "z...@c3commsystems.com" <z...@c3commsystems.com>,
usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AGC in E310 via UHD?
Message-ID: <04189069-593a-124b-e06e-07b5cbf92...@ettus.com>
Content-Type: text/plain; charset=windows-1252
By default, slow AGC is enabled. We also expose a fast mode, which you
will get if you set the corresponding property to 'fast'. The property
depends on the channel you're on, but look at the property tree with
$ uhd_usrp_probe --tree
and find the one that ends in ...gain/agc/mode/value. The corresponding
property with the list of options is ...gain/agc/mode/options.
You can't do this through multi_usrp, though. You need to get a device
pointer:
/* Assume USRP is a multi_usrp object: */
USRP->get_device()->get_tree()->access<std::string>("/path/to/gain/agc/mode/value").set("fast");
Cheers,
Martin
On 10/15/2016 06:55 PM, zcao--- via USRP-users wrote:
> Hi,
>
> The UHD has a method
>
> uhd::usrp::multi_usrp::set_rx_agc(bool enable, size chan);
>
> AD9361 has four AGC modes. If we enable AGC on E310 using the above
> method, which AGC mode is deployed in AD9361? In addition, AGC in AD9361
> relies on several overload threshold, which is programmable. Are these
> thresholds programmable via UHD?
>
> Thanks,
> Zhongren
>
> Zhongren Cao, Ph.D.
> *C-3 Comm Systems, LLC.*
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
------------------------------
Message: 4
Date: Tue, 18 Oct 2016 14:48:32 +0200
From: Marcus M?ller <marcus.muel...@ettus.com>
To: ??? <2012301650...@whu.edu.cn>, usrp-users
<usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] [SPAM] Re: Modify the FPGA in X300
Message-ID: <a5a02e59-c2e4-1911-0351-cd6d4fdbf...@ettus.com>
Content-Type: text/plain; charset=utf-8
Hi Tan,
> Dear Marcus
> Thank you for your help.I am using the x300 to collect GPS data.When I
> go outdoors to collect GPS data?I have to use laptop.So I can just link to
> the pc across GE.The GE limite the transmission speed.
ah, so the link to the PC is the bottleneck
> To improve Sampling rate,I hope to the usrp output 2bit samples to the PC.
Well, GPS is actually one of the rare cases where such minimal sample
depths are possible indeed
> Can I achieve it by modifying the fpga code?
Yes!
> If it is possible to ahieve it ,should I build system follow the FPGA maunal
> in http://files.ettus.com/manual/md_usrp3_build_instructions.html?
Yes; mostly, however, you should definitely look into getting started
with RFNoC. Doing so will allow you to simply write an AXI4 module that
takes in 16bit samples and spits out 2bit samples, and UHD will still
take care of everything around.
Then again: if you're already modifying the FPGA image, it might be
worthwhile thinking about which signals and bandwidths you're interested
in. Could you elaborate on that?
Best regards,
Marcus
------------------------------
Message: 5
Date: Tue, 18 Oct 2016 11:05:12 -0400
From: Zhongren Cao <z...@c3commsystems.com>
To: Martin Braun <martin.br...@ettus.com>
Cc: Emanuel via USRP-users <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] AGC in E310 via UHD?
Message-ID: <f7b768ce-7a50-404e-a712-28e89ca3d...@c3commsystems.com>
Content-Type: text/plain; charset="windows-1252"
Martin,
Thank you very much for the response.
I tried the following command
root@ettus-e3xx-sg1:~# uhd_usrp_probe --string
/mboards/0/dboards/A/rx_frontends/A/gain/agc/mode/value
A segment of the output is in the following:
-- Performing timer loopback test... pass
-- [0/Radio_0] e3xx_radio_ctrl_impl::_update_enables()
-- [0/Radio_0] e3xx_radio_ctrl_impl::_update_gpio_state()
-- end of e300_impl()
slow
-- Loading FPGA image: /usr/share/uhd/images/usrp_e3xx_fpga_idle.bit... done
root@ettus-e3xx-sg1:~#
We can see the word ?slow?, which corroborates your answer. However, we have
also developed a simple function to directly read AD9361 registers via the
timed SPI interface. The value we read from Reg 0FA is 0xE0. According to the
AD9361 register map, this value corresponds to the manual AGC model, instead of
the slow mode.
AD9361 has four AGC modes ? manual, fast, slow and hybrid. I tried to read the
value for property ?/gain/age/mode/options using uhd_usrp_probe, but I could?t
get it. If I use ?string, it returns a very long but unreadable screen output.
If I use ?range, the program responded with error msg: ?Error: ValueError:
meta-range is not monotonic?. So how could we probe the available options
without reading the source code?
Thanks,
Zhongren
> On Oct 17, 2016, at 1:49 PM, Martin Braun <martin.br...@ettus.com> wrote:
>
> By default, slow AGC is enabled. We also expose a fast mode, which you
> will get if you set the corresponding property to 'fast'. The property
> depends on the channel you're on, but look at the property tree with
>
> $ uhd_usrp_probe --tree
>
> and find the one that ends in ...gain/agc/mode/value. The corresponding
> property with the list of options is ...gain/agc/mode/options.
>
> You can't do this through multi_usrp, though. You need to get a device
> pointer:
>
> /* Assume USRP is a multi_usrp object: */
> USRP->get_device()->get_tree()->access<std::string>("/path/to/gain/agc/mode/value").set("fast");
>
>
> Cheers,
> Martin
>
> On 10/15/2016 06:55 PM, zcao--- via USRP-users wrote:
>> Hi,
>>
>> The UHD has a method
>>
>> uhd::usrp::multi_usrp::set_rx_agc(bool enable, size chan);
>>
>> AD9361 has four AGC modes. If we enable AGC on E310 using the above
>> method, which AGC mode is deployed in AD9361? In addition, AGC in AD9361
>> relies on several overload threshold, which is programmable. Are these
>> thresholds programmable via UHD?
>>
>> Thanks,
>> Zhongren
>>
>> Zhongren Cao, Ph.D.
>> *C-3 Comm Systems, LLC.*
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
Zhongren Cao, Ph.D.
C-3 Comm Systems
Vienna, VA 22181
(703) 829 0588
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Message: 6
Date: Tue, 18 Oct 2016 08:26:51 -0700
From: Martin Braun <martin.br...@ettus.com>
To: "'USRP-users@lists.ettus.com'" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] AGC in E310 via UHD?
Message-ID: <63173802-107c-c28f-cca2-bd488cb7d...@ettus.com>
Content-Type: text/plain; charset=windows-1252
On 10/18/2016 08:05 AM, Zhongren Cao wrote:
> AD9361 has four AGC modes ? manual, fast, slow and hybrid. I tried to
> read the value for property ?/gain/age/mode/options using
> uhd_usrp_probe, but I could?t get it. If I use ?string, it returns a
> very long but unreadable screen output. If I use ?range, the program
> responded with error msg: ?Error: ValueError: meta-range is not
> monotonic?. So how could we probe the available options without reading
> the source code?
The options are 'slow' and 'fast'. On maint and master, you can do
$ uhd_usrp_probe --string /path/ --vector
...on rfnoc-devel, this option will also soon be available.
As for your comment on the reg value being wrong, we'll need to check that.
Cheers,
Martin
------------------------------
Message: 7
Date: Tue, 18 Oct 2016 12:17:44 +0200
From: Oscar S?nchez <odsanch...@gmail.com>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] B205mini-I clock source
Message-ID:
<CAGRFgoGV5Fs=q9k8o6f5a_v+ybmyumznepdflzjke4jwr_8...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi all,
I have the following setup:
* B205mini-I: tx
* B200mini: rx
As far as I know, the only difference between both boards is the FPGA (x75
or x150).
I want to set the same reference clk. Thus, in GRC for both boards: Mb0:
Clock Source = External. I see that the python script generated is ok :
self.uhd_usrp_source_0.set_clock_source("external", 0)
self.uhd_usrp_sink_0_0.set_clock_source("external", 0)
However, S1 (external source selected) and S0 (external source locked) are
never ON in my B205mini-I.
In B200mini everything is OK: S1 is on as soon as the system starts, and S0
is on when a 10MHz clock is plugged in J3.
I see that the correct bitsreams are downloaded (usrp_b200mini_fpga.bin and
usrp_b205mini_fpga.bin).
Regarding the verilog sources in b2xxmini the files are named b205*, so I
suppose the only difference in the bitstream generation is the device
selection.
Is there something else I have to consider to make my B205 accept an
external clk?
Thanks in advance,
Oscar
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