Hi,
In vhdl I create many times entity is like below:
entity HALFADDER is
port(
A, B : in bit;
SUM, CARRY: out bit);
end entity HALFADDER;
When I want to use this port into another bigger file
(for example a full-adder ) I need in VHDL to
create a component from it.
This then looks like
Eric Leenman wrote:
entity HALFADDER is
port(
A, B : in bit;
SUM, CARRY: out bit);
end entity HALFADDER;
component HALFADDER
port(
A, B : in bit;
SUM, CARRY: out bit);
end component;
Is it then easy to replace the first and last line of these 5 lines of
entity code to 5
