[PATCHv2] qemu: make default_write_config use mask table

Change much of hw/pci to use symbolic constants and a table-driven design: add a mask table with writable bits set and readonly bits unset. Detect change by comparing original and new registers. This makes it easy to support capabilities where read-only/writeable bit layout differs between

[PATCH 00/11] qemu: MSI-X support

Here is the port of MSI-X support patches to upstream qemu. Anthony, you said you are willing to borrow a few cycles to help MSI-X go in through QEMU - could you please comment or commit? This patchset adds generic support for MSI-X, adds implementation in APIC, and uses MSI-X in virtio-net. At

[PATCH 01/11] qemu: make default_write_config use mask table

Change much of hw/pci to use symbolic constants and a table-driven design: add a mask table with writable bits set and readonly bits unset. Detect change by comparing original and new registers. This makes it easy to support capabilities where read-only/writeable bit layout differs between

[PATCH 03/11] qemu: add routines to manage PCI capabilities

Add routines to manage PCI capability list. First user will be MSI-X. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/pci.c | 98 -- hw/pci.h | 18 +++- 2 files changed, 106 insertions(+), 10 deletions(-) diff

[PATCH 02/11] qemu: capability bits in pci save/restore

Add support for capability bits in save/restore for pci. These will be used for MSI, where the capability might be present or not as requested by user, which does not map well into a single version number. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/pci.c | 14 --

[PATCH 04/11] qemu: helper routines for pci access.

Add inline routines for convenient access to pci devices with correct (little) endianness. Will be used by MSI-X support. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/pci.h | 30 +++--- 1 files changed, 27 insertions(+), 3 deletions(-) diff --git a/hw/pci.h

[PATCH 05/11] qemu: MSI-X support functions

Add functions implementing MSI-X support. First user will be virtio-pci. Note that platform must set a flag to declare MSI supported. For PC this will be set by APIC. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- Makefile.target |2 +- hw/msix.c | 423

[PATCH 06/11] qemu: add flag to disable MSI-X by default

Add global flag to disable MSI-X by default. This is useful primarily to make images loadable by older qemu (without msix). Even when MSI-X is disabled by flag, you can still load images that have MSI-X enabled. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/msix.c |3 +++

[PATCH 07/11] qemu: minimal MSI/MSI-X implementation for PC

Implement MSI support in APIC. Note that MSI and MMIO APIC registers are at the same memory location, but actually not on the global bus: MSI is on PCI bus, APIC is connected directly to the CPU. We map them on the global bus at the same address which happens to work because MSI registers are

[PATCH 08/11] qemu: add support for resizing regions

Make it possible to resize PCI regions. This will be used by virtio with MSI-X, where the region size depends on whether MSI-X is enabled, and can change across load/save. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/pci.c | 54

[PATCH 10/11] qemu: MSI-X support in virtio PCI

This enables actual support for MSI-X in virtio PCI. First user will be virtio-net. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/virtio-pci.c | 152 -- 1 files changed, 112 insertions(+), 40 deletions(-) diff --git

[PATCH 09/11] qemu: virtio support for many interrupt vectors

Extend virtio to support many interrupt vectors, and rearrange code in preparation for multi-vector support (mostly move reset out to bindings, because we will have to reset the vectors in transport-specific code). Actual bindings in pci, and use in net, to follow. Load and save are not connected

[PATCH] qemu: virtio save/load bindings

Implement bindings for virtio save/load. Use them in virtio pci. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- Is anyone working to fill in load/save bindings so that saving virtio devices works? Here's a trivial patch to do this (this one is on top of my MSI-X patchset). Comments?

lguest PAE

Jeremy, I fixed the code following your comments (hope you still remember). I'd like to ask you again about this one: /* Found in switcher.S */ extern unsigned long default_idt_entries[]; diff --git a/arch/x86/include/asm/lguest_hcall.h b/arch/x86/include/asm/lguest_hcall.h index

Re: [Qemu-devel] [PATCH 04/11] qemu: helper routines for pci access.

Just a minor comment. How about to add pci_[sg]et_byte() for consistency? On Mon, May 25, 2009 at 03:25:33PM +0300, Michael S. Tsirkin wrote: Add inline routines for convenient access to pci devices with correct (little) endianness. Will be used by MSI-X support. Signed-off-by: Michael S.