Title: [286892] trunk/Source/_javascript_Core
- Revision
- 286892
- Author
- mikh...@igalia.com
- Date
- 2021-12-10 17:17:19 -0800 (Fri, 10 Dec 2021)
Log Message
[JSC][32bit] Add callee save registers for MIPS
https://bugs.webkit.org/show_bug.cgi?id=233766
Reviewed by Mark Lam.
This patch enables callee save registers for mips, which fixes an
assertion violation from the call frame shufflers in some tests if
jsc was built with assertions enabled (either debug or release+assert
mode).
* jit/RegisterSet.cpp:
(JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
(JSC::RegisterSet::dfgCalleeSaveRegisters):
Modified Paths
Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (286891 => 286892)
--- trunk/Source/_javascript_Core/ChangeLog 2021-12-11 01:10:47 UTC (rev 286891)
+++ trunk/Source/_javascript_Core/ChangeLog 2021-12-11 01:17:19 UTC (rev 286892)
@@ -1,3 +1,19 @@
+2021-12-10 Mikhail R. Gadelha <mikh...@igalia.com>
+
+ [JSC][32bit] Add callee save registers for MIPS
+ https://bugs.webkit.org/show_bug.cgi?id=233766
+
+ Reviewed by Mark Lam.
+
+ This patch enables callee save registers for mips, which fixes an
+ assertion violation from the call frame shufflers in some tests if
+ jsc was built with assertions enabled (either debug or release+assert
+ mode).
+
+ * jit/RegisterSet.cpp:
+ (JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
+ (JSC::RegisterSet::dfgCalleeSaveRegisters):
+
2021-12-10 Yusuke Suzuki <ysuz...@apple.com>
[JSC] isTaggedJSCCodePtrImpl does not have proper implementation for JITCage & JITCode combination
Modified: trunk/Source/_javascript_Core/jit/RegisterSet.cpp (286891 => 286892)
--- trunk/Source/_javascript_Core/jit/RegisterSet.cpp 2021-12-11 01:10:47 UTC (rev 286891)
+++ trunk/Source/_javascript_Core/jit/RegisterSet.cpp 2021-12-11 01:17:19 UTC (rev 286892)
@@ -213,7 +213,7 @@
result.set(GPRInfo::regCS5);
result.set(GPRInfo::regCS6);
#endif
-#elif CPU(ARM_THUMB2)
+#elif CPU(ARM_THUMB2) || CPU(MIPS)
result.set(GPRInfo::regCS0);
result.set(GPRInfo::regCS1);
#elif CPU(ARM64) || CPU(RISCV64)
@@ -223,9 +223,6 @@
static_assert(GPRInfo::regCS9 == GPRInfo::notCellMaskRegister, "");
result.set(GPRInfo::regCS8);
result.set(GPRInfo::regCS9);
-#elif CPU(MIPS)
- result.set(GPRInfo::regCS0);
- result.set(GPRInfo::regCS1);
#else
UNREACHABLE_FOR_PLATFORM();
#endif
@@ -253,7 +250,7 @@
result.set(GPRInfo::regCS5);
result.set(GPRInfo::regCS6);
#endif
-#elif CPU(ARM_THUMB2)
+#elif CPU(ARM_THUMB2) || CPU(MIPS)
result.set(GPRInfo::regCS0);
result.set(GPRInfo::regCS1);
#elif CPU(ARM64)
@@ -261,7 +258,6 @@
static_assert(GPRInfo::regCS9 == GPRInfo::notCellMaskRegister, "");
result.set(GPRInfo::regCS8);
result.set(GPRInfo::regCS9);
-#elif CPU(MIPS)
#else
UNREACHABLE_FOR_PLATFORM();
#endif
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