# HG changeset patch # User Vignesh Vijayakumar<vign...@multicorewareinc.com> # Date 1511948305 -19800 # Wed Nov 29 15:08:25 2017 +0530 # Node ID 9f2c4a0d09f3405f9c28cd3ebf229617c2278681 # Parent 3e2058cec6c6f4ad49d92f9df7fbc110a54f4b4b x86: AVX512 interp_8tap_vert_sp_32xN
Size | AVX2 performance | AVX512 performance ---------------------------------------------- 32x8 | 11.19x | 21.10x 32x16 | 12.71x | 21.91x 32x24 | 11.99x | 22.26x 32x32 | 12.52x | 22.42x 32x64 | 12.61x | 22.54x diff -r 3e2058cec6c6 -r 9f2c4a0d09f3 source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Wed Nov 29 14:51:30 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Wed Nov 29 15:08:25 2017 +0530 @@ -2881,6 +2881,11 @@ p.pu[LUMA_64x48].luma_vsp = PFX(interp_8tap_vert_sp_64x48_avx512); p.pu[LUMA_64x64].luma_vsp = PFX(interp_8tap_vert_sp_64x64_avx512); p.pu[LUMA_48x64].luma_vsp = PFX(interp_8tap_vert_sp_48x64_avx512); + p.pu[LUMA_32x64].luma_vsp = PFX(interp_8tap_vert_sp_32x64_avx512); + p.pu[LUMA_32x32].luma_vsp = PFX(interp_8tap_vert_sp_32x32_avx512); + p.pu[LUMA_32x24].luma_vsp = PFX(interp_8tap_vert_sp_32x24_avx512); + p.pu[LUMA_32x16].luma_vsp = PFX(interp_8tap_vert_sp_32x16_avx512); + p.pu[LUMA_32x8].luma_vsp = PFX(interp_8tap_vert_sp_32x8_avx512); p.cu[BLOCK_8x8].dct = PFX(dct8_avx512); p.cu[BLOCK_8x8].idct = PFX(idct8_avx512); diff -r 3e2058cec6c6 -r 9f2c4a0d09f3 source/common/x86/ipfilter8.asm --- a/source/common/x86/ipfilter8.asm Wed Nov 29 14:51:30 2017 +0530 +++ b/source/common/x86/ipfilter8.asm Wed Nov 29 15:08:25 2017 +0530 @@ -246,9 +246,8 @@ const interp4_hps_shuf_avx512, dq 0, 4, 1, 5, 2, 6, 3, 7 const interp4_hps_store_16xN_avx512, dq 0, 2, 1, 3, 4, 6, 5, 7 const interp8_hps_store_avx512, dq 0, 1, 4, 5, 2, 3, 6, 7 - +const interp8_vsp_store_avx512, dq 0, 2, 4, 6, 1, 3, 5, 7 SECTION .text - cextern pb_128 cextern pw_1 cextern pw_32 @@ -13357,8 +13356,7 @@ PROCESS_LUMA_VERT_SS_24x8_AVX512 RET %endif - -%macro PROCESS_LUMA_VERT_SS_32x2_AVX512 0 +%macro PROCESS_LUMA_VERT_S_32x2_AVX512 1 movu m1, [r0] ;0 row movu m3, [r0 + r1] ;1 row punpcklwd m0, m1, m3 @@ -13409,23 +13407,38 @@ pmaddwd m14, m18 punpckhwd m12, m13 pmaddwd m12, m18 - paddd m8, m14 paddd m4, m12 - paddd m0, m8 - paddd m1, m4 - movu m12, [r6 + 4 * r1] ; 8 row punpcklwd m14, m13, m12 pmaddwd m14, m18 punpckhwd m13, m12 pmaddwd m13, m18 - paddd m10, m14 paddd m11, m13 + + paddd m0, m8 + paddd m1, m4 paddd m2, m10 paddd m3, m11 - +%ifidn %1, sp + paddd m0, m19 + paddd m1, m19 + paddd m2, m19 + paddd m3, m19 + + psrad m0, 12 + psrad m1, 12 + psrad m2, 12 + psrad m3, 12 + + packssdw m0, m1 + packssdw m2, m3 + packuswb m0, m2 + vpermq m0, m20, m0 + movu [r2], ym0 + vextracti32x8 [r2 + r3], m0, 1 +%else psrad m0, 6 psrad m1, 6 psrad m2, 6 @@ -13433,18 +13446,17 @@ packssdw m0, m1 packssdw m2, m3 - movu [r2], m0 movu [r2 + r3], m2 +%endif %endmacro ;----------------------------------------------------------------------------------------------------------------- ; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx) ;----------------------------------------------------------------------------------------------------------------- -%macro FILTER_VER_SS_LUMA_32xN_AVX512 1 +%macro FILTER_VER_S_LUMA_32xN_AVX512 2 INIT_ZMM avx512 -cglobal interp_8tap_vert_ss_32x%1, 5, 8, 19 +cglobal interp_8tap_vert_%1_32x%2, 5, 8, 21 add r1d, r1d - add r3d, r3d lea r7, [3 * r1] sub r0, r7 shl r4d, 8 @@ -13461,26 +13473,36 @@ mova m17, [r5 + 2 * mmsize] mova m18, [r5 + 3 * mmsize] %endif - -%rep %1/2 - 1 - PROCESS_LUMA_VERT_SS_32x2_AVX512 +%ifidn %1, sp + vbroadcasti32x4 m19, [pd_526336] + mova m20, [interp8_vsp_store_avx512] +%else + add r3d, r3d +%endif + +%rep %2/2 - 1 + PROCESS_LUMA_VERT_S_32x2_AVX512 %1 lea r0, [r0 + 2 * r1] lea r2, [r2 + 2 * r3] %endrep - PROCESS_LUMA_VERT_SS_32x2_AVX512 + PROCESS_LUMA_VERT_S_32x2_AVX512 %1 RET %endmacro %if ARCH_X86_64 - FILTER_VER_SS_LUMA_32xN_AVX512 8 - FILTER_VER_SS_LUMA_32xN_AVX512 16 - FILTER_VER_SS_LUMA_32xN_AVX512 32 - FILTER_VER_SS_LUMA_32xN_AVX512 24 - FILTER_VER_SS_LUMA_32xN_AVX512 64 -%endif - + FILTER_VER_S_LUMA_32xN_AVX512 ss, 8 + FILTER_VER_S_LUMA_32xN_AVX512 ss, 16 + FILTER_VER_S_LUMA_32xN_AVX512 ss, 32 + FILTER_VER_S_LUMA_32xN_AVX512 ss, 24 + FILTER_VER_S_LUMA_32xN_AVX512 ss, 64 + FILTER_VER_S_LUMA_32xN_AVX512 sp, 8 + FILTER_VER_S_LUMA_32xN_AVX512 sp, 16 + FILTER_VER_S_LUMA_32xN_AVX512 sp, 32 + FILTER_VER_S_LUMA_32xN_AVX512 sp, 24 + FILTER_VER_S_LUMA_32xN_AVX512 sp, 64 +%endif %macro PROCESS_LUMA_VERT_SS_48x4_AVX512 0 - PROCESS_LUMA_VERT_SS_32x2_AVX512 + PROCESS_LUMA_VERT_S_32x2_AVX512 ss movu m1, [r0 + 2 * r1] movu m3, [r0 + r7] punpcklwd m0, m1, m3 _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel