# HG changeset patch # User Vignesh Vijayakumar<vign...@multicorewareinc.com> # Date 1512018320 -19800 # Thu Nov 30 10:35:20 2017 +0530 # Node ID a78e09e144582bd52c52d3475aa1922fc2ae8893 # Parent 3e14c3f607d0f9ec6dd3735d21fc2e698217fe71 x86: AVX512 interp_8tap_vert_sp_16xN
Size | AVX2 performance | AVX512 performance ---------------------------------------------- 16x4 | 9.68x | 16.45x 16x8 | 11.69x | 16.93x 16x16 | 13.26x | 18.58x 16x32 | 12.96x | 19.23x 16x64 | 13.12x | 16.84x diff -r 3e14c3f607d0 -r a78e09e14458 source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Thu Nov 30 16:00:14 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Thu Nov 30 10:35:20 2017 +0530 @@ -5002,7 +5002,12 @@ p.pu[LUMA_64x48].luma_vpp = PFX(interp_8tap_vert_pp_64x48_avx512); p.pu[LUMA_64x32].luma_vpp = PFX(interp_8tap_vert_pp_64x32_avx512); p.pu[LUMA_64x16].luma_vpp = PFX(interp_8tap_vert_pp_64x16_avx512); - + p.pu[LUMA_16x4].luma_vsp = PFX(interp_8tap_vert_sp_16x4_avx512); + p.pu[LUMA_16x8].luma_vsp = PFX(interp_8tap_vert_sp_16x8_avx512); + p.pu[LUMA_16x12].luma_vsp = PFX(interp_8tap_vert_sp_16x12_avx512); + p.pu[LUMA_16x16].luma_vsp = PFX(interp_8tap_vert_sp_16x16_avx512); + p.pu[LUMA_16x32].luma_vsp = PFX(interp_8tap_vert_sp_16x32_avx512); + p.pu[LUMA_16x64].luma_vsp = PFX(interp_8tap_vert_sp_16x64_avx512); p.pu[LUMA_32x64].luma_vsp = PFX(interp_8tap_vert_sp_32x64_avx512); p.pu[LUMA_32x32].luma_vsp = PFX(interp_8tap_vert_sp_32x32_avx512); p.pu[LUMA_32x24].luma_vsp = PFX(interp_8tap_vert_sp_32x24_avx512); diff -r 3e14c3f607d0 -r a78e09e14458 source/common/x86/ipfilter8.asm --- a/source/common/x86/ipfilter8.asm Thu Nov 30 16:00:14 2017 +0530 +++ b/source/common/x86/ipfilter8.asm Thu Nov 30 10:35:20 2017 +0530 @@ -12985,8 +12985,7 @@ FILTER_VER_SS_LUMA_8xN_AVX512 16 FILTER_VER_SS_LUMA_8xN_AVX512 32 %endif - -%macro PROCESS_LUMA_VERT_SS_16x4_AVX512 0 +%macro PROCESS_LUMA_VERT_S_16x4_AVX512 1 movu ym1, [r0] movu ym3, [r0 + r1] vinserti32x8 m1, [r0 + 2 * r1], 1 @@ -13062,7 +13061,26 @@ paddd m11, m13 paddd m2, m10 paddd m3, m11 - +%ifidn %1, sp + paddd m0, m19 + paddd m1, m19 + paddd m2, m19 + paddd m3, m19 + + psrad m0, 12 + psrad m1, 12 + psrad m2, 12 + psrad m3, 12 + + packssdw m0, m1 + packssdw m2, m3 + packuswb m0, m2 + vpermq m0, m20, m0 + movu [r2], xm0 + vextracti32x4 [r2 + r3], m0, 2 + vextracti32x4 [r2 + 2 * r3], m0, 1 + vextracti32x4 [r2 + r5], m0, 3 +%else psrad m0, 6 psrad m1, 6 psrad m2, 6 @@ -13075,15 +13093,15 @@ movu [r2 + r3], ym2 vextracti32x8 [r2 + 2 * r3], m0, 1 vextracti32x8 [r2 + r5], m2, 1 +%endif %endmacro ;----------------------------------------------------------------------------------------------------------------- ; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx) ;----------------------------------------------------------------------------------------------------------------- -%macro FILTER_VER_SS_LUMA_16xN_AVX512 1 +%macro FILTER_VER_S_LUMA_16xN_AVX512 2 INIT_ZMM avx512 -cglobal interp_8tap_vert_ss_16x%1, 5, 8, 19 +cglobal interp_8tap_vert_%1_16x%2, 5, 8, 21 add r1d, r1d - add r3d, r3d lea r7, [3 * r1] sub r0, r7 shl r4d, 8 @@ -13100,28 +13118,39 @@ mova m17, [r5 + 2 * mmsize] mova m18, [r5 + 3 * mmsize] %endif +%ifidn %1, sp + vbroadcasti32x4 m19, [pd_526336] + mova m20, [interp8_vsp_store_avx512] +%else + add r3d, r3d +%endif lea r5, [3 * r3] -%rep %1/4 - 1 - PROCESS_LUMA_VERT_SS_16x4_AVX512 +%rep %2/4 - 1 + PROCESS_LUMA_VERT_S_16x4_AVX512 %1 lea r0, [r0 + 4 * r1] lea r2, [r2 + 4 * r3] %endrep - PROCESS_LUMA_VERT_SS_16x4_AVX512 + PROCESS_LUMA_VERT_S_16x4_AVX512 %1 RET %endmacro %if ARCH_X86_64 - FILTER_VER_SS_LUMA_16xN_AVX512 4 - FILTER_VER_SS_LUMA_16xN_AVX512 8 - FILTER_VER_SS_LUMA_16xN_AVX512 12 - FILTER_VER_SS_LUMA_16xN_AVX512 16 - FILTER_VER_SS_LUMA_16xN_AVX512 32 - FILTER_VER_SS_LUMA_16xN_AVX512 64 -%endif - + FILTER_VER_S_LUMA_16xN_AVX512 ss, 4 + FILTER_VER_S_LUMA_16xN_AVX512 ss, 8 + FILTER_VER_S_LUMA_16xN_AVX512 ss, 12 + FILTER_VER_S_LUMA_16xN_AVX512 ss, 16 + FILTER_VER_S_LUMA_16xN_AVX512 ss, 32 + FILTER_VER_S_LUMA_16xN_AVX512 ss, 64 + FILTER_VER_S_LUMA_16xN_AVX512 sp, 4 + FILTER_VER_S_LUMA_16xN_AVX512 sp, 8 + FILTER_VER_S_LUMA_16xN_AVX512 sp, 12 + FILTER_VER_S_LUMA_16xN_AVX512 sp, 16 + FILTER_VER_S_LUMA_16xN_AVX512 sp, 32 + FILTER_VER_S_LUMA_16xN_AVX512 sp, 64 +%endif %macro PROCESS_LUMA_VERT_SS_24x8_AVX512 0 - PROCESS_LUMA_VERT_SS_16x4_AVX512 + PROCESS_LUMA_VERT_S_16x4_AVX512 ss lea r4, [r6 + 4 * r1] lea r8, [r4 + 4 * r1] movu ym1, [r6] _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel