# HG changeset patch # User Vignesh Vijayakumar # Date 1504173085 -19800 # Thu Aug 31 15:21:25 2017 +0530 # Node ID c726239a07580fd13c4177f0206d615ee02c5975 # Parent 1fb1948309a0a9218a07e060300b9d5a7ff58321 x86: AVX512 interp_4tap_horiz_pp_24xN for high bit depth
i444 24x32 AVX2 performance : 8.85x AVX512 performance : 19.37x diff -r 1fb1948309a0 -r c726239a0758 source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Thu Aug 31 14:54:18 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Thu Aug 31 15:21:25 2017 +0530 @@ -2367,6 +2367,7 @@ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_hpp = PFX(interp_4tap_horiz_pp_32x16_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_hpp = PFX(interp_4tap_horiz_pp_32x24_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_hpp = PFX(interp_4tap_horiz_pp_32x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_hpp = PFX(interp_4tap_horiz_pp_24x32_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_hpp = PFX(interp_4tap_horiz_pp_8x4_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_hpp = PFX(interp_4tap_horiz_pp_8x8_avx512); @@ -2383,6 +2384,7 @@ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_hpp = PFX(interp_4tap_horiz_pp_32x32_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_hpp = PFX(interp_4tap_horiz_pp_32x48_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_hpp = PFX(interp_4tap_horiz_pp_32x64_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_hpp = PFX(interp_4tap_horiz_pp_24x64_avx512); p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_hpp = PFX(interp_4tap_horiz_pp_8x4_avx512); p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_hpp = PFX(interp_4tap_horiz_pp_8x8_avx512); @@ -2404,6 +2406,7 @@ p.chroma[X265_CSP_I444].pu[LUMA_64x48].filter_hpp = PFX(interp_4tap_horiz_pp_64x48_avx512); p.chroma[X265_CSP_I444].pu[LUMA_64x64].filter_hpp = PFX(interp_4tap_horiz_pp_64x64_avx512); p.chroma[X265_CSP_I444].pu[LUMA_48x64].filter_hpp = PFX(interp_4tap_horiz_pp_48x64_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_hpp = PFX(interp_4tap_horiz_pp_24x32_avx512); } } diff -r 1fb1948309a0 -r c726239a0758 source/common/x86/ipfilter16.asm --- a/source/common/x86/ipfilter16.asm Thu Aug 31 14:54:18 2017 +0530 +++ b/source/common/x86/ipfilter16.asm Thu Aug 31 15:21:25 2017 +0530 @@ -5161,6 +5161,103 @@ vextracti32x8 [r2 + r3], m7, 1 %endmacro +%macro PROCESS_IPFILTER_CHROMA_PP_24x4_AVX512 0 + ; register map + ; m0 , m1 interpolate coeff + ; m2 , m3 shuffle order table + ; m4 - pd_32 + ; m5 - zero + ; m6 - pw_pixel_max + + movu ym7, [r0] + vinserti32x8 m7, [r0 + r1], 1 + movu ym8, [r0 + 8] + vinserti32x8 m8, [r0 + r1 + 8], 1 + + pshufb m9, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m9, m1 + paddd m7, m9 + paddd m7, m4 + psrad m7, 6 + + pshufb m9, m8, m3 + pshufb m8, m2 + pmaddwd m8, m0 + pmaddwd m9, m1 + paddd m8, m9 + paddd m8, m4 + psrad m8, 6 + + packusdw m7, m8 + CLIPW m7, m5, m6 + pshufb m7, m10 + movu [r2], ym7 + vextracti32x8 [r2 + r3], m7, 1 + + movu ym7, [r0 + 2 * r1] + vinserti32x8 m7, [r0 + r6], 1 + movu ym8, [r0 + 2 * r1 + 8] + vinserti32x8 m8, [r0 + r6 + 8], 1 + + pshufb m9, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m9, m1 + paddd m7, m9 + paddd m7, m4 + psrad m7, 6 + + pshufb m9, m8, m3 + pshufb m8, m2 + pmaddwd m8, m0 + pmaddwd m9, m1 + paddd m8, m9 + paddd m8, m4 + psrad m8, 6 + + packusdw m7, m8 + CLIPW m7, m5, m6 + pshufb m7, m10 + movu [r2 + 2 * r3], ym7 + vextracti32x8 [r2 + r7], m7, 1 + + movu xm7, [r0 + mmsize/2] + vinserti32x4 m7, [r0 + r1 + mmsize/2], 1 + vinserti32x4 m7, [r0 + 2 * r1 + mmsize/2], 2 + vinserti32x4 m7, [r0 + r6 + mmsize/2], 3 + + pshufb m9, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m9, m1 + paddd m7, m9 + paddd m7, m4 + psrad m7, 6 + + movu xm8, [r0 + mmsize/2 + 8] + vinserti32x4 m8, [r0 + r1 + mmsize/2 + 8], 1 + vinserti32x4 m8, [r0 + 2 * r1 + mmsize/2 + 8], 2 + vinserti32x4 m8, [r0 + r6 + mmsize/2 + 8], 3 + + pshufb m9, m8, m3 + pshufb m8, m2 + pmaddwd m8, m0 + pmaddwd m9, m1 + paddd m8, m9 + paddd m8, m4 + psrad m8, 6 + + packusdw m7, m8 + CLIPW m7, m5, m6 + pshufb m7, m10 + movu [r2 + mmsize/2], xm7 + vextracti32x4 [r2 + r3 + mmsize/2], m7, 1 + vextracti32x4 [r2 + 2 * r3 + mmsize/2], m7, 2 + vextracti32x4 [r2 + r7 + mmsize/2], m7, 3 +%endmacro + %macro PROCESS_IPFILTER_CHROMA_PP_32x2_AVX512 0 ; register map ; m0 , m1 interpolate coeff @@ -5514,6 +5611,42 @@ IPFILTER_CHROMA_AVX512_16xN 64 INIT_ZMM avx512 +%macro IPFILTER_CHROMA_AVX512_24xN 1 +cglobal interp_4tap_horiz_pp_24x%1, 5,8,11 + add r1d, r1d + add r3d, r3d + sub r0, 2 + mov r4d, r4m + lea r6, [3 * r1] + lea r7, [3 * r3] +%ifdef PIC + lea r5, [tab_ChromaCoeff] + vpbroadcastd m0, [r5 + r4 * 8] + vpbroadcastd m1, [r5 + r4 * 8 + 4] +%else + vpbroadcastd m0, [tab_ChromaCoeff + r4 * 8] + vpbroadcastd m1, [tab_ChromaCoeff + r4 * 8 + 4] +%endif + vbroadcasti32x8 m2, [interp8_hpp_shuf1_load_avx512] + vbroadcasti32x8 m3, [interp8_hpp_shuf2_load_avx512] + vbroadcasti32x8 m4, [pd_32] + pxor m5, m5 + vbroadcasti32x8 m6, [pw_pixel_max] + vbroadcasti32x8 m10, [interp8_hpp_shuf1_store_avx512] + +%rep %1/4 - 1 + PROCESS_IPFILTER_CHROMA_PP_24x4_AVX512 + lea r0, [r0 + 4 * r1] + lea r2, [r2 + 4 * r3] +%endrep + PROCESS_IPFILTER_CHROMA_PP_24x4_AVX512 + RET +%endmacro + +IPFILTER_CHROMA_AVX512_24xN 32 +IPFILTER_CHROMA_AVX512_24xN 64 + +INIT_ZMM avx512 %macro IPFILTER_CHROMA_AVX512_32xN 1 cglobal interp_4tap_horiz_pp_32x%1, 5,6,11 add r1d, r1d _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel