# HG changeset patch # User Jayashri Murugan <jayas...@multicorewareinc.com> # Date 1510569160 -19800 # Mon Nov 13 16:02:40 2017 +0530 # Node ID df3c576cd32c50b0412ad3d70eeebfe8fb511da1 # Parent ab41c6957bc2f359e5df82f9936c3fd00a5d2ea5 x86: AVX512 interp_4tap_horiz_ps_24xN for high bit depth
Color Space i420 Size | AVX2 performance | AVX512 performance ---------------------------------------------- 24x32 | 24.21x | 34.11x Color Space i422 Size | AVX2 performance | AVX512 performance ---------------------------------------------- 24x64 | 24.99x | 35.13x Color Space i444 Size | AVX2 performance | AVX512 performance ---------------------------------------------- 24x32 | 24.40x | 34.42x diff -r ab41c6957bc2 -r df3c576cd32c source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Thu Apr 05 18:09:10 2018 -0700 +++ b/source/common/x86/asm-primitives.cpp Mon Nov 13 16:02:40 2017 +0530 @@ -2897,6 +2897,10 @@ p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_hps = PFX(interp_4tap_horiz_ps_8x16_avx512); p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_hps = PFX(interp_4tap_horiz_ps_8x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_hps = PFX(interp_4tap_horiz_ps_24x32_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_hps = PFX(interp_4tap_horiz_ps_24x64_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_hps = PFX(interp_4tap_horiz_ps_24x32_avx512); + } #endif } diff -r ab41c6957bc2 -r df3c576cd32c source/common/x86/ipfilter16.asm --- a/source/common/x86/ipfilter16.asm Thu Apr 05 18:09:10 2018 -0700 +++ b/source/common/x86/ipfilter16.asm Mon Nov 13 16:02:40 2017 +0530 @@ -7479,6 +7479,228 @@ IPFILTER_CHROMA_PS_AVX512_8xN 32 IPFILTER_CHROMA_PS_AVX512_8xN 64 %endif + +%macro PROCESS_IPFILTER_CHROMA_PS_24x4_AVX512 0 + ; register map + ; m0 , m1 - interpolate coeff + ; m2 , m3 - shuffle order table + ; m4 - INTERP_OFFSET_PS + ; m5 - shuffle store order table + + movu ym6, [r0] + vinserti32x8 m6, [r0 + r1], 1 + movu ym7, [r0 + 8] + vinserti32x8 m7, [r0 + r1 + 8], 1 + + pshufb m8, m6, m3 + pshufb m6, m2 + pmaddwd m6, m0 + pmaddwd m8, m1 + paddd m6, m8 + paddd m6, m4 + psrad m6, INTERP_SHIFT_PS + + pshufb m8, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m8, m1 + paddd m7, m8 + paddd m7, m4 + psrad m7, INTERP_SHIFT_PS + + packssdw m6, m7 + pshufb m6, m5 + movu [r2], ym6 + vextracti32x8 [r2 + r3], m6, 1 + + movu ym6, [r0 + 2 * r1] + vinserti32x8 m6, [r0 + r6], 1 + movu ym7, [r0 + 2 * r1 + 8] + vinserti32x8 m7, [r0 + r6 + 8], 1 + + pshufb m8, m6, m3 + pshufb m6, m2 + pmaddwd m6, m0 + pmaddwd m8, m1 + paddd m6, m8 + paddd m6, m4 + psrad m6, INTERP_SHIFT_PS + + pshufb m8, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m8, m1 + paddd m7, m8 + paddd m7, m4 + psrad m7, INTERP_SHIFT_PS + + packssdw m6, m7 + pshufb m6, m5 + movu [r2 + 2 * r3], ym6 + vextracti32x8 [r2 + r7], m6, 1 + + movu xm6, [r0 + mmsize/2] + vinserti32x4 m6, [r0 + r1 + mmsize/2], 1 + vinserti32x4 m6, [r0 + 2 * r1 + mmsize/2], 2 + vinserti32x4 m6, [r0 + r6 + mmsize/2], 3 + + pshufb m8, m6, m3 + pshufb m6, m2 + pmaddwd m6, m0 + pmaddwd m8, m1 + paddd m6, m8 + paddd m6, m4 + psrad m6, INTERP_SHIFT_PS + + movu xm7, [r0 + mmsize/2 + 8] + vinserti32x4 m7, [r0 + r1 + mmsize/2 + 8], 1 + vinserti32x4 m7, [r0 + 2 * r1 + mmsize/2 + 8], 2 + vinserti32x4 m7, [r0 + r6 + mmsize/2 + 8], 3 + + pshufb m8, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m8, m1 + paddd m7, m8 + paddd m7, m4 + psrad m7, INTERP_SHIFT_PS + + packssdw m6, m7 + pshufb m6, m5 + movu [r2 + mmsize/2], xm6 + vextracti32x4 [r2 + r3 + mmsize/2], m6, 1 + vextracti32x4 [r2 + 2 * r3 + mmsize/2], m6, 2 + vextracti32x4 [r2 + r7 + mmsize/2], m6, 3 +%endmacro + +%macro PROCESS_IPFILTER_CHROMA_PS_24x3_AVX512 0 + movu ym6, [r0] + vinserti32x8 m6, [r0 + r1], 1 + movu ym7, [r0 + 8] + vinserti32x8 m7, [r0 + r1 + 8], 1 + + pshufb m8, m6, m3 + pshufb m6, m2 + pmaddwd m6, m0 + pmaddwd m8, m1 + paddd m6, m8 + paddd m6, m4 + psrad m6, INTERP_SHIFT_PS + + pshufb m8, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m8, m1 + paddd m7, m8 + paddd m7, m4 + psrad m7, INTERP_SHIFT_PS + + packssdw m6, m7 + pshufb m6, m5 + movu [r2], ym6 + vextracti32x8 [r2 + r3], m6, 1 + + movu ym6, [r0 + 2 * r1] + movu ym7, [r0 + 2 * r1 + 8] + + pshufb ym8, ym6, ym3 + pshufb ym6, ym2 + pmaddwd ym6, ym0 + pmaddwd ym8, ym1 + paddd ym6, ym8 + paddd ym6, ym4 + psrad ym6, INTERP_SHIFT_PS + + pshufb ym8, ym7, ym3 + pshufb ym7, ym2 + pmaddwd ym7, ym0 + pmaddwd ym8, ym1 + paddd ym7, ym8 + paddd ym7, ym4 + psrad ym7, INTERP_SHIFT_PS + + packssdw ym6, ym7 + pshufb ym6, ym5 + movu [r2 + 2 * r3], ym6 + + movu xm6, [r0 + mmsize/2] + vinserti32x4 m6, [r0 + r1 + mmsize/2], 1 + vinserti32x4 m6, [r0 + 2 * r1 + mmsize/2], 2 + + pshufb m8, m6, m3 + pshufb m6, m2 + pmaddwd m6, m0 + pmaddwd m8, m1 + paddd m6, m8 + paddd m6, m4 + psrad m6, INTERP_SHIFT_PS + + movu xm7, [r0 + mmsize/2 + 8] + vinserti32x4 m7, [r0 + r1 + mmsize/2 + 8], 1 + vinserti32x4 m7, [r0 + 2 * r1 + mmsize/2 + 8], 2 + + pshufb m8, m7, m3 + pshufb m7, m2 + pmaddwd m7, m0 + pmaddwd m8, m1 + paddd m7, m8 + paddd m7, m4 + psrad m7, INTERP_SHIFT_PS + + packssdw m6, m7 + pshufb m6, m5 + movu [r2 + mmsize/2], xm6 + vextracti32x4 [r2 + r3 + mmsize/2], m6, 1 + vextracti32x4 [r2 + 2 * r3 + mmsize/2], m6, 2 +%endmacro + +%macro IPFILTER_CHROMA_PS_AVX512_24xN 1 +INIT_ZMM avx512 +cglobal interp_4tap_horiz_ps_24x%1, 4,9,9 + add r1d, r1d + add r3d, r3d + mov r4d, r4m + mov r5d, r5m + + lea r6, [3 * r1] + lea r7, [3 * r3] +%ifdef PIC + lea r8, [tab_ChromaCoeff] + vpbroadcastd m0, [r8 + r4 * 8] + vpbroadcastd m1, [r8 + r4 * 8 + 4] +%else + vpbroadcastd m0, [tab_ChromaCoeff + r4 * 8] + vpbroadcastd m1, [tab_ChromaCoeff + r4 * 8 + 4] +%endif + vbroadcasti32x8 m2, [interp8_hpp_shuf1_load_avx512] + vbroadcasti32x8 m3, [interp8_hpp_shuf2_load_avx512] + vbroadcasti32x4 m4, [INTERP_OFFSET_PS] + vbroadcasti32x8 m5,[interp8_hpp_shuf1_store_avx512] + + mov r8d, %1 + sub r0, 2 + test r5d, r5d + jz .loop + sub r0, r1 + add r8d, 3 + PROCESS_IPFILTER_CHROMA_PS_24x3_AVX512 + lea r0, [r0 + r6] + lea r2, [r2 + r7] + sub r8d, 3 + +.loop: + PROCESS_IPFILTER_CHROMA_PS_24x4_AVX512 + lea r0, [r0 + 4 * r1] + lea r2, [r2 + 4 * r3] + sub r8d, 4 + jnz .loop + RET +%endmacro + +%if ARCH_X86_64 +IPFILTER_CHROMA_PS_AVX512_24xN 32 +IPFILTER_CHROMA_PS_AVX512_24xN 64 +%endif ;------------------------------------------------------------------------------------------------------------- ; avx512 chroma_hps code end ;------------------------------------------------------------------------------------------------------------- _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel