# HG changeset patch
# User Vignesh Vijayakumar<vign...@multicorewareinc.com>
# Date 1512465067 -19800
# Tue Dec 05 14:41:07 2017 +0530
# Node ID f92128e41ac3c1da210c1c665d97061539821aaf
# Parent ca6bb5919227672e0cf98b785acf099531c32945
x86: AVX512 interp_8tap_vert_pp_16xN and interp_8tap_vert_ps_16xN for high bit
depth
luma_vpp
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 8.32x | 13.14x
16x8 | 10.69x | 15.14x
16x12 | 11.62x | 15.94x
16x16 | 12.19x | 15.97x
16x32 | 12.24x | 16.59x
16x64 | 12.57x | 16.50x
luma_vps
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 8.04x | 15.37x
16x8 | 9.72x | 14.97x
16x12 | 10.47x | 14.71x
16x16 | 9.79x | 15.21x
16x32 | 9.66x | 15.60x
16x64 | 11.16x | 15.67x
diff -r ca6bb5919227 -r f92128e41ac3 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Dec 05 13:28:42 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Dec 05 14:41:07 2017 +0530
@@ -2882,6 +2882,12 @@
p.pu[LUMA_64x64].luma_vsp = PFX(interp_8tap_vert_sp_64x64_avx512);
p.pu[LUMA_48x64].luma_vsp = PFX(interp_8tap_vert_sp_48x64_avx512);
+ p.pu[LUMA_16x4].luma_vpp = PFX(interp_8tap_vert_pp_16x4_avx512);
+ p.pu[LUMA_16x8].luma_vpp = PFX(interp_8tap_vert_pp_16x8_avx512);
+ p.pu[LUMA_16x12].luma_vpp = PFX(interp_8tap_vert_pp_16x12_avx512);
+ p.pu[LUMA_16x16].luma_vpp = PFX(interp_8tap_vert_pp_16x16_avx512);
+ p.pu[LUMA_16x32].luma_vpp = PFX(interp_8tap_vert_pp_16x32_avx512);
+ p.pu[LUMA_16x64].luma_vpp = PFX(interp_8tap_vert_pp_16x64_avx512);
p.pu[LUMA_32x8].luma_vpp = PFX(interp_8tap_vert_pp_32x8_avx512);
p.pu[LUMA_32x16].luma_vpp = PFX(interp_8tap_vert_pp_32x16_avx512);
p.pu[LUMA_32x32].luma_vpp = PFX(interp_8tap_vert_pp_32x32_avx512);
@@ -2892,6 +2898,12 @@
p.pu[LUMA_64x48].luma_vpp = PFX(interp_8tap_vert_pp_64x48_avx512);
p.pu[LUMA_64x64].luma_vpp = PFX(interp_8tap_vert_pp_64x64_avx512);
+ p.pu[LUMA_16x4].luma_vps = PFX(interp_8tap_vert_ps_16x4_avx512);
+ p.pu[LUMA_16x8].luma_vps = PFX(interp_8tap_vert_ps_16x8_avx512);
+ p.pu[LUMA_16x12].luma_vps = PFX(interp_8tap_vert_ps_16x12_avx512);
+ p.pu[LUMA_16x16].luma_vps = PFX(interp_8tap_vert_ps_16x16_avx512);
+ p.pu[LUMA_16x32].luma_vps = PFX(interp_8tap_vert_ps_16x32_avx512);
+ p.pu[LUMA_16x64].luma_vps = PFX(interp_8tap_vert_ps_16x64_avx512);
p.pu[LUMA_32x8].luma_vps = PFX(interp_8tap_vert_ps_32x8_avx512);
p.pu[LUMA_32x16].luma_vps = PFX(interp_8tap_vert_ps_32x16_avx512);
p.pu[LUMA_32x32].luma_vps = PFX(interp_8tap_vert_ps_32x32_avx512);
diff -r ca6bb5919227 -r f92128e41ac3 source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Tue Dec 05 13:28:42 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Tue Dec 05 14:41:07 2017 +0530
@@ -12930,6 +12930,169 @@
;-------------------------------------------------------------------------------------------------------------
;avx512 luma_vpp and luma_vps code start
;-------------------------------------------------------------------------------------------------------------
+%macro PROCESS_LUMA_VERT_P_16x4_AVX512 1
+ lea r6, [r0 + 4 * r1]
+ movu ym1, [r0]
+ movu ym3, [r0 + r1]
+ vinserti32x8 m1, [r0 + 2 * r1], 1
+ vinserti32x8 m3, [r0 + r7], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m15
+ punpckhwd m1, m3
+ pmaddwd m1, m15
+
+ movu ym4, [r0 + 2 * r1]
+ vinserti32x8 m4, [r0 + 4 * r1], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m15
+ punpckhwd m3, m4
+ pmaddwd m3, m15
+
+ movu ym5, [r0 + r7]
+ vinserti32x8 m5, [r6 + r1], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m16
+ punpckhwd m4, m5
+ pmaddwd m4, m16
+
+ paddd m0, m6
+ paddd m1, m4
+
+ movu ym4, [r6]
+ vinserti32x8 m4, [r6 + 2 * r1], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m16
+ punpckhwd m5, m4
+ pmaddwd m5, m16
+
+ paddd m2, m6
+ paddd m3, m5
+
+ lea r4, [r6 + 4 * r1]
+ movu ym11, [r6 + r1]
+ vinserti32x8 m11, [r6 + r7], 1
+ punpcklwd m8, m4, m11
+ pmaddwd m8, m17
+ punpckhwd m4, m11
+ pmaddwd m4, m17
+
+ movu ym12, [r6 + 2 * r1]
+ vinserti32x8 m12, [r4], 1
+ punpcklwd m10, m11, m12
+ pmaddwd m10, m17
+ punpckhwd m11, m12
+ pmaddwd m11, m17
+
+ movu ym13, [r6 + r7]
+ vinserti32x8 m13, [r4 + r1], 1
+ punpcklwd m14, m12, m13
+ pmaddwd m14, m18
+ punpckhwd m12, m13
+ pmaddwd m12, m18
+
+ paddd m8, m14
+ paddd m4, m12
+ paddd m0, m8
+ paddd m1, m4
+
+ movu ym12, [r4]
+ vinserti32x8 m12, [r4 + 2 * r1], 1
+ punpcklwd m14, m13, m12
+ pmaddwd m14, m18
+ punpckhwd m13, m12
+ pmaddwd m13, m18
+
+ paddd m10, m14
+ paddd m11, m13
+ paddd m2, m10
+ paddd m3, m11
+
+ paddd m0, m19
+ paddd m1, m19
+ paddd m2, m19
+ paddd m3, m19
+
+%ifidn %1, pp
+ psrad m0, INTERP_SHIFT_PP
+ psrad m1, INTERP_SHIFT_PP
+ psrad m2, INTERP_SHIFT_PP
+ psrad m3, INTERP_SHIFT_PP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ CLIPW2 m0, m2, m20,
m21
+%else
+ psrad m0, INTERP_SHIFT_PS
+ psrad m1, INTERP_SHIFT_PS
+ psrad m2, INTERP_SHIFT_PS
+ psrad m3, INTERP_SHIFT_PS
+
+ packssdw m0, m1
+ packssdw m2, m3
+%endif
+
+ movu [r2], ym0
+ movu [r2 + r3], ym2
+ vextracti32x8 [r2 + 2 * r3], m0, 1
+ vextracti32x8 [r2 + r8], m2, 1
+%endmacro
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst,
intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_P_LUMA_16xN_AVX512 2
+INIT_ZMM avx512
+cglobal interp_8tap_vert_%1_16x%2, 5, 9, 22
+ add r1d, r1d
+ add r3d, r3d
+ shl r4d, 8
+%ifdef PIC
+ lea r5, [tab_LumaCoeffVer_avx512]
+ mova m15, [r5 + r4]
+ mova m16, [r5 + r4 + 1 * mmsize]
+ mova m17, [r5 + r4 + 2 * mmsize]
+ mova m18, [r5 + r4 + 3 * mmsize]
+%else
+ lea r5, [tab_LumaCoeffVer_avx512 + r4]
+ mova m15, [r5]
+ mova m16, [r5 + 1 * mmsize]
+ mova m17, [r5 + 2 * mmsize]
+ mova m18, [r5 + 3 * mmsize]
+%endif
+%ifidn %1, pp
+ vbroadcasti32x4 m19, [INTERP_OFFSET_PP]
+ pxor m20, m20
+ vbroadcasti32x8 m21, [pw_pixel_max]
+%else
+ vbroadcasti32x4 m19, [INTERP_OFFSET_PS]
+%endif
+ lea r7, [3 * r1]
+ lea r8, [3 * r3]
+ sub r0, r7
+
+%rep %2/4 - 1
+ PROCESS_LUMA_VERT_P_16x4_AVX512 %1
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_LUMA_VERT_P_16x4_AVX512 %1
+ RET
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_VER_P_LUMA_16xN_AVX512 ps, 4
+ FILTER_VER_P_LUMA_16xN_AVX512 ps, 8
+ FILTER_VER_P_LUMA_16xN_AVX512 ps, 12
+ FILTER_VER_P_LUMA_16xN_AVX512 ps, 16
+ FILTER_VER_P_LUMA_16xN_AVX512 ps, 32
+ FILTER_VER_P_LUMA_16xN_AVX512 ps, 64
+ FILTER_VER_P_LUMA_16xN_AVX512 pp, 4
+ FILTER_VER_P_LUMA_16xN_AVX512 pp, 8
+ FILTER_VER_P_LUMA_16xN_AVX512 pp, 12
+ FILTER_VER_P_LUMA_16xN_AVX512 pp, 16
+ FILTER_VER_P_LUMA_16xN_AVX512 pp, 32
+ FILTER_VER_P_LUMA_16xN_AVX512 pp, 64
+%endif
+
%macro PROCESS_LUMA_VERT_P_32x2_AVX512 1
movu m1, [r0]
;0 row
movu m3, [r0 + r1]
;1 row
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