# HG changeset patch
# User Vignesh Vijayakumar<vign...@multicorewareinc.com>
# Date 1510035839 -19800
# Tue Nov 07 11:53:59 2017 +0530
# Node ID ae3775aa94f3acceb7d43ce7db2df6f8be6c6912
# Parent 9df6f8ae51300ebbb9d0941f7fc1cce1fdef4e94
x86: AVX512 interp_4tap_vert_ps_8xN for high bit depth
i444
Size | AVX2 performance | AVX512 performance
----------------------------------------------
8x8 | 19.97x | 28.50x
8x16 | 22.32x | 27.74x
8x32 | 21.73x | 29.04x
diff -r 9df6f8ae5130 -r ae3775aa94f3 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Nov 07 11:20:54 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Nov 07 11:53:59 2017 +0530
@@ -2670,6 +2670,9 @@
p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vpp =
PFX(interp_4tap_vert_pp_8x8_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vpp =
PFX(interp_4tap_vert_pp_8x16_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vpp =
PFX(interp_4tap_vert_pp_8x32_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vps =
PFX(interp_4tap_vert_ps_8x8_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vps =
PFX(interp_4tap_vert_ps_8x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vps =
PFX(interp_4tap_vert_ps_8x32_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vpp =
PFX(interp_4tap_vert_pp_32x16_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vpp =
PFX(interp_4tap_vert_pp_32x32_avx512);
@@ -2693,6 +2696,10 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vpp =
PFX(interp_4tap_vert_pp_8x16_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vpp =
PFX(interp_4tap_vert_pp_8x32_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vpp =
PFX(interp_4tap_vert_pp_8x64_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vps =
PFX(interp_4tap_vert_ps_8x8_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vps =
PFX(interp_4tap_vert_ps_8x16_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vps =
PFX(interp_4tap_vert_ps_8x32_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vps =
PFX(interp_4tap_vert_ps_8x64_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vpp =
PFX(interp_4tap_vert_pp_32x8_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vpp =
PFX(interp_4tap_vert_pp_32x16_avx512);
@@ -2715,6 +2722,9 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vpp =
PFX(interp_4tap_vert_pp_8x8_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vpp =
PFX(interp_4tap_vert_pp_8x16_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vpp =
PFX(interp_4tap_vert_pp_8x32_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vps =
PFX(interp_4tap_vert_ps_8x8_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vps =
PFX(interp_4tap_vert_ps_8x16_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vps =
PFX(interp_4tap_vert_ps_8x32_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vpp =
PFX(interp_4tap_vert_pp_24x32_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_vpp =
PFX(interp_4tap_vert_pp_24x64_avx512);
diff -r 9df6f8ae5130 -r ae3775aa94f3 source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Tue Nov 07 11:20:54 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Tue Nov 07 11:53:59 2017 +0530
@@ -7342,6 +7342,133 @@
RET
%endif
+%macro PROCESS_CHROMA_VERT_PS_8x8_AVX512 0
+ movu xm1, [r0]
+ lea r6, [r0 + 2 * r1]
+ lea r8, [r0 + 4 * r1]
+ lea r9, [r8 + 2 * r1]
+ vinserti32x4 m1, [r6], 1
+ vinserti32x4 m1, [r8], 2
+ vinserti32x4 m1, [r9], 3
+ movu xm3, [r0 + r1]
+ vinserti32x4 m3, [r6 + r1], 1
+ vinserti32x4 m3, [r8 + r1], 2
+ vinserti32x4 m3, [r9 + r1], 3
+ punpcklwd m0, m1, m3
+ pmaddwd m0, [r5]
+ punpckhwd m1, m3
+ pmaddwd m1, [r5]
+
+ movu xm4, [r0 + 2 * r1]
+ vinserti32x4 m4, [r6 + 2 * r1], 1
+ vinserti32x4 m4, [r8 + 2 * r1], 2
+ vinserti32x4 m4, [r9 + 2 * r1], 3
+ punpcklwd m2, m3, m4
+ pmaddwd m2, [r5]
+ punpckhwd m3, m4
+ pmaddwd m3, [r5]
+
+ movu xm5, [r0 + r10]
+ vinserti32x4 m5, [r6 + r10], 1
+ vinserti32x4 m5, [r8 + r10], 2
+ vinserti32x4 m5, [r9 + r10], 3
+ punpcklwd m6, m4, m5
+ pmaddwd m6, [r5 + mmsize]
+ paddd m0, m6
+ punpckhwd m4, m5
+ pmaddwd m4, [r5 + mmsize]
+ paddd m1, m4
+
+ movu xm4, [r0 + 4 * r1]
+ vinserti32x4 m4, [r6 + 4 * r1], 1
+ vinserti32x4 m4, [r8 + 4 * r1], 2
+ vinserti32x4 m4, [r9 + 4 * r1], 3
+ punpcklwd m6, m5, m4
+ pmaddwd m6, [r5 + mmsize]
+ paddd m2, m6
+ punpckhwd m5, m4
+ pmaddwd m5, [r5 + mmsize]
+ paddd m3, m5
+
+ paddd m0, m7
+ paddd m1, m7
+ paddd m2, m7
+ paddd m3, m7
+
+ psrad m0, INTERP_SHIFT_PS
+ psrad m1, INTERP_SHIFT_PS
+ psrad m2, INTERP_SHIFT_PS
+ psrad m3, INTERP_SHIFT_PS
+
+ packssdw m0, m1
+ packssdw m2, m3
+ movu [r2], xm0
+ movu [r2 + r3], xm2
+ vextracti32x4 [r2 + 2 * r3], m0, 1
+ vextracti32x4 [r2 + r7], m2, 1
+ lea r2, [r2 + 4 * r3]
+ vextracti32x4 [r2], m0, 2
+ vextracti32x4 [r2 + r3], m2, 2
+ vextracti32x4 [r2 + 2 * r3], m0, 3
+ vextracti32x4 [r2 + r7], m2, 3
+%endmacro
+
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst,
intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%if ARCH_X86_64
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ps_8x8, 5, 11, 8
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV_avx512]
+ lea r5, [r5 + r4]
+%else
+ lea r5, [tab_ChromaCoeffV_avx512 + r4]
+%endif
+ vbroadcasti32x4 m7, [INTERP_OFFSET_PS]
+ lea r10, [3 * r1]
+ lea r7, [3 * r3]
+ PROCESS_CHROMA_VERT_PS_8x8_AVX512
+ RET
+%endif
+
+%macro FILTER_VER_PS_CHROMA_8xN_AVX512 1
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ps_8x%1, 5, 11, 8
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV_avx512]
+ lea r5, [r5 + r4]
+%else
+ lea r5, [tab_ChromaCoeffV_avx512 + r4]
+%endif
+ vbroadcasti32x4 m7, [INTERP_OFFSET_PS]
+ lea r10, [3 * r1]
+ lea r7, [3 * r3]
+%rep %1/8 - 1
+ PROCESS_CHROMA_VERT_PS_8x8_AVX512
+ lea r0, [r8 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_CHROMA_VERT_PS_8x8_AVX512
+ RET
+%endmacro
+
+%if ARCH_X86_64
+FILTER_VER_PS_CHROMA_8xN_AVX512 16
+FILTER_VER_PS_CHROMA_8xN_AVX512 32
+FILTER_VER_PS_CHROMA_8xN_AVX512 64
+%endif
+
%macro PROCESS_CHROMA_VERT_PS_16x4_AVX512 0
movu ym1, [r0]
lea r6, [r0 + 2 * r1]
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