# HG changeset patch
# User Vignesh Vijayakumar<vign...@multicorewareinc.com>
# Date 1511505545 -19800
# Fri Nov 24 12:09:05 2017 +0530
# Node ID 47b99c09008b1921881b0dfa00d80cce1f8d15eb
# Parent ecaf36f641dd1428d556f172e83cf7078f0287fb
x86: AVX512 interp_8tap_vert_sp_24x32 and interp_8tap_vert_ss_24x32
luma_vss
AVX2 performance : 10.98x
AVX512 performance : 16.36x
luma_vsp
AVX2 performance : 12.19x
AVX512 performance : 17.20x
diff -r ecaf36f641dd -r 47b99c09008b source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Fri Nov 24 11:34:33 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Fri Nov 24 12:09:05 2017 +0530
@@ -2844,6 +2844,7 @@
p.pu[LUMA_16x16].luma_vss = PFX(interp_8tap_vert_ss_16x16_avx512);
p.pu[LUMA_16x32].luma_vss = PFX(interp_8tap_vert_ss_16x32_avx512);
p.pu[LUMA_16x64].luma_vss = PFX(interp_8tap_vert_ss_16x64_avx512);
+ p.pu[LUMA_24x32].luma_vss = PFX(interp_8tap_vert_ss_24x32_avx512);
p.pu[LUMA_32x8].luma_vss = PFX(interp_8tap_vert_ss_32x8_avx512);
p.pu[LUMA_32x16].luma_vss = PFX(interp_8tap_vert_ss_32x16_avx512);
p.pu[LUMA_32x32].luma_vss = PFX(interp_8tap_vert_ss_32x32_avx512);
@@ -2864,6 +2865,7 @@
p.pu[LUMA_16x16].luma_vsp = PFX(interp_8tap_vert_sp_16x16_avx512);
p.pu[LUMA_16x32].luma_vsp = PFX(interp_8tap_vert_sp_16x32_avx512);
p.pu[LUMA_16x64].luma_vsp = PFX(interp_8tap_vert_sp_16x64_avx512);
+ p.pu[LUMA_24x32].luma_vsp = PFX(interp_8tap_vert_sp_24x32_avx512);
p.pu[LUMA_32x8].luma_vsp = PFX(interp_8tap_vert_sp_32x8_avx512);
p.pu[LUMA_32x16].luma_vsp = PFX(interp_8tap_vert_sp_32x16_avx512);
p.pu[LUMA_32x32].luma_vsp = PFX(interp_8tap_vert_sp_32x32_avx512);
diff -r ecaf36f641dd -r 47b99c09008b source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Fri Nov 24 11:34:33 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Fri Nov 24 12:09:05 2017 +0530
@@ -11134,6 +11134,284 @@
FILTER_VER_S_LUMA_16xN_AVX512 sp, 64
%endif
+%macro PROCESS_LUMA_VERT_S_24x8_AVX512 1
+ PROCESS_LUMA_VERT_S_16x4_AVX512 %1
+ lea r4, [r6 + 4 * r1]
+ lea r8, [r4 + 4 * r1]
+ movu ym1, [r6]
+ movu ym3, [r6 + r1]
+ vinserti32x8 m1, [r6 + 2 * r1], 1
+ vinserti32x8 m3, [r6 + r7], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m15
+ punpckhwd m1, m3
+ pmaddwd m1, m15
+
+ movu ym4, [r6 + 2 * r1]
+ vinserti32x8 m4, [r4], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m15
+ punpckhwd m3, m4
+ pmaddwd m3, m15
+
+ movu ym5, [r6 + r7]
+ vinserti32x8 m5, [r4 + r1], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m16
+ punpckhwd m4, m5
+ pmaddwd m4, m16
+
+ paddd m0, m6
+ paddd m1, m4
+
+ movu ym4, [r4]
+ vinserti32x8 m4, [r4 + 2 * r1], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m16
+ punpckhwd m5, m4
+ pmaddwd m5, m16
+
+ paddd m2, m6
+ paddd m3, m5
+
+ movu ym11, [r4 + r1]
+ vinserti32x8 m11, [r4 + r7], 1
+ punpcklwd m8, m4, m11
+ pmaddwd m8, m17
+ punpckhwd m4, m11
+ pmaddwd m4, m17
+
+ movu ym12, [r4 + 2 * r1]
+ vinserti32x8 m12, [r4 + 4 * r1], 1
+ punpcklwd m10, m11, m12
+ pmaddwd m10, m17
+ punpckhwd m11, m12
+ pmaddwd m11, m17
+
+ movu ym13, [r4 + r7]
+ vinserti32x8 m13, [r8 + r1], 1
+ punpcklwd m14, m12, m13
+ pmaddwd m14, m18
+ punpckhwd m12, m13
+ pmaddwd m12, m18
+
+ paddd m8, m14
+ paddd m4, m12
+ paddd m0, m8
+ paddd m1, m4
+
+ movu ym12, [r4 + 4 * r1]
+ vinserti32x8 m12, [r8 + 2 * r1], 1
+ punpcklwd m14, m13, m12
+ pmaddwd m14, m18
+ punpckhwd m13, m12
+ pmaddwd m13, m18
+
+ paddd m10, m14
+ paddd m11, m13
+ paddd m2, m10
+ paddd m3, m11
+
+%ifidn %1, sp
+ paddd m0, m19
+ paddd m1, m19
+ paddd m2, m19
+ paddd m3, m19
+
+ psrad m0, INTERP_SHIFT_SP
+ psrad m1, INTERP_SHIFT_SP
+ psrad m2, INTERP_SHIFT_SP
+ psrad m3, INTERP_SHIFT_SP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ CLIPW2 m0, m2, m20,
m21
+%else
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+
+ packssdw m0, m1
+ packssdw m2, m3
+%endif
+ lea r9, [r2 + 4 * r3]
+ movu [r9], ym0
+ movu [r9 + r3], ym2
+ vextracti32x8 [r9 + 2 * r3], m0, 1
+ vextracti32x8 [r9 + r5], m2, 1
+
+ movu xm1, [r0 + mmsize/2]
+ vinserti32x4 m1, [r0 + 2 * r1 + mmsize/2],
1
+ vinserti32x4 m1, [r0 + 4 * r1 + mmsize/2],
2
+ vinserti32x4 m1, [r6 + 2 * r1 + mmsize/2],
3
+ movu xm3, [r0 + r1 + mmsize/2]
+ vinserti32x4 m3, [r0 + r7 + mmsize/2],
1
+ vinserti32x4 m3, [r6 + r1 + mmsize/2],
2
+ vinserti32x4 m3, [r6 + r7 + mmsize/2],
3
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m15
+ punpckhwd m1, m3
+ pmaddwd m1, m15
+
+ movu xm4, [r0 + 2 * r1 + mmsize/2]
+ vinserti32x4 m4, [r0 + 4 * r1 + mmsize/2],
1
+ vinserti32x4 m4, [r6 + 2 * r1 + mmsize/2],
2
+ vinserti32x4 m4, [r6 + 4 * r1 + mmsize/2],
3
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m15
+ punpckhwd m3, m4
+ pmaddwd m3, m15
+
+ movu xm5, [r0 + r7 + mmsize/2]
+ vinserti32x4 m5, [r6 + r1 + mmsize/2],
1
+ vinserti32x4 m5, [r6 + r7 + mmsize/2],
2
+ vinserti32x4 m5, [r4 + r1 + mmsize/2],
3
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m16
+ punpckhwd m4, m5
+ pmaddwd m4, m16
+
+ paddd m0, m6
+ paddd m1, m4
+
+ movu xm4, [r0 + 4 * r1 + mmsize/2]
+ vinserti32x4 m4, [r6 + 2 * r1 + mmsize/2],
1
+ vinserti32x4 m4, [r6 + 4 * r1 + mmsize/2],
2
+ vinserti32x4 m4, [r4 + 2 * r1 + mmsize/2],
3
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m16
+ punpckhwd m5, m4
+ pmaddwd m5, m16
+
+ paddd m2, m6
+ paddd m3, m5
+
+ movu xm11, [r6 + r1 + mmsize/2]
+ vinserti32x4 m11, [r6 + r7 + mmsize/2],
1
+ vinserti32x4 m11, [r4 + r1 + mmsize/2],
2
+ vinserti32x4 m11, [r4 + r7 + mmsize/2],
3
+ punpcklwd m8, m4, m11
+ pmaddwd m8, m17
+ punpckhwd m4, m11
+ pmaddwd m4, m17
+
+ movu xm12, [r6 + 2 * r1 + mmsize/2]
+ vinserti32x4 m12, [r6 + 4 * r1 + mmsize/2],
1
+ vinserti32x4 m12, [r4 + 2 * r1 + mmsize/2],
2
+ vinserti32x4 m12, [r4 + 4 * r1 + mmsize/2],
3
+ punpcklwd m10, m11, m12
+ pmaddwd m10, m17
+ punpckhwd m11, m12
+ pmaddwd m11, m17
+
+ movu xm13, [r6 + r7 + mmsize/2]
+ vinserti32x4 m13, [r4 + r1 + mmsize/2],
1
+ vinserti32x4 m13, [r4 + r7 + mmsize/2],
2
+ vinserti32x4 m13, [r8 + r1 + mmsize/2],
3
+ punpcklwd m14, m12, m13
+ pmaddwd m14, m18
+ punpckhwd m12, m13
+ pmaddwd m12, m18
+
+ paddd m8, m14
+ paddd m4, m12
+ paddd m0, m8
+ paddd m1, m4
+
+ movu xm12, [r6 + 4 * r1 + mmsize/2]
+ vinserti32x4 m12, [r4 + 2 * r1 + mmsize/2],
1
+ vinserti32x4 m12, [r4 + 4 * r1 + mmsize/2],
2
+ vinserti32x4 m12, [r8 + 2 * r1 + mmsize/2],
3
+ punpcklwd m14, m13, m12
+ pmaddwd m14, m18
+ punpckhwd m13, m12
+ pmaddwd m13, m18
+
+ paddd m10, m14
+ paddd m11, m13
+ paddd m2, m10
+ paddd m3, m11
+
+%ifidn %1, sp
+ paddd m0, m19
+ paddd m1, m19
+ paddd m2, m19
+ paddd m3, m19
+
+ psrad m0, INTERP_SHIFT_SP
+ psrad m1, INTERP_SHIFT_SP
+ psrad m2, INTERP_SHIFT_SP
+ psrad m3, INTERP_SHIFT_SP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ CLIPW2 m0, m2, m20,
m21
+%else
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+
+ packssdw m0, m1
+ packssdw m2, m3
+%endif
+
+ movu [r2 + mmsize/2], xm0
+ movu [r2 + r3 + mmsize/2], xm2
+ vextracti32x4 [r2 + 2 * r3 + mmsize/2], m0, 1
+ vextracti32x4 [r2 + r5 + mmsize/2], m2, 1
+ lea r2, [r2 + 4 * r3]
+ vextracti32x4 [r2 + mmsize/2], m0, 2
+ vextracti32x4 [r2 + r3 + mmsize/2], m2, 2
+ vextracti32x4 [r2 + 2 * r3 + mmsize/2], m0, 3
+ vextracti32x4 [r2 + r5 + mmsize/2], m2, 3
+%endmacro
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst,
intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_S_LUMA_24x32_AVX512 1
+INIT_ZMM avx512
+cglobal interp_8tap_vert_%1_24x32, 5, 10, 22
+ add r1d, r1d
+ add r3d, r3d
+ lea r7, [3 * r1]
+ sub r0, r7
+ shl r4d, 8
+%ifdef PIC
+ lea r5, [tab_LumaCoeffVer_avx512]
+ mova m15, [r5 + r4]
+ mova m16, [r5 + r4 + 1 * mmsize]
+ mova m17, [r5 + r4 + 2 * mmsize]
+ mova m18, [r5 + r4 + 3 * mmsize]
+%else
+ lea r5, [tab_LumaCoeffVer_avx512 + r4]
+ mova m15, [r5]
+ mova m16, [r5 + 1 * mmsize]
+ mova m17, [r5 + 2 * mmsize]
+ mova m18, [r5 + 3 * mmsize]
+%endif
+%ifidn %1, sp
+ vbroadcasti32x4 m19, [INTERP_OFFSET_SP]
+ pxor m20, m20
+ vbroadcasti32x8 m21, [pw_pixel_max]
+%endif
+ lea r5, [3 * r3]
+
+%rep 3
+ PROCESS_LUMA_VERT_S_24x8_AVX512 %1
+ lea r0, [r4]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_LUMA_VERT_S_24x8_AVX512 %1
+ RET
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_VER_S_LUMA_24x32_AVX512 ss
+ FILTER_VER_S_LUMA_24x32_AVX512 sp
+%endif
+
%macro PROCESS_LUMA_VERT_S_32x2_AVX512 1
movu m1, [r0]
;0 row
movu m3, [r0 + r1]
;1 row
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