# HG changeset patch # User Jayashri Murugan <jayas...@multicorewareinc.com> # Date 1512627824 -19800 # Thu Dec 07 11:53:44 2017 +0530 # Node ID e2a41cef45ae06d73c0c17d99a853df6e81562ee # Parent 862e490b929710720e0066335c95a6e8951b2194 x86: AVX512 interp_8tap_vert_ps_64xN
Size | AVX2 performance | AVX512 performance ---------------------------------------------- 64x16 | 23.97x | 36.34x 64x32 | 24.21x | 34.68x 64x48 | 24.58x | 35.31x 64x64 | 24.65x | 35.40x diff -r 862e490b9297 -r e2a41cef45ae source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Thu Dec 07 11:53:44 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Thu Dec 07 11:53:44 2017 +0530 @@ -5193,7 +5193,10 @@ //p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vps = PFX(interp_4tap_vert_ps_16x12_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vps = PFX(interp_4tap_vert_ps_16x4_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vps = PFX(interp_4tap_vert_ps_16x64_avx512); - + p.pu[LUMA_64x16].luma_vps = PFX(interp_8tap_vert_ps_64x16_avx512); + p.pu[LUMA_64x32].luma_vps = PFX(interp_8tap_vert_ps_64x32_avx512); + p.pu[LUMA_64x48].luma_vps = PFX(interp_8tap_vert_ps_64x48_avx512); + p.pu[LUMA_64x64].luma_vps = PFX(interp_8tap_vert_ps_64x64_avx512); } #endif } diff -r 862e490b9297 -r e2a41cef45ae source/common/x86/ipfilter8.asm --- a/source/common/x86/ipfilter8.asm Thu Dec 07 11:53:44 2017 +0530 +++ b/source/common/x86/ipfilter8.asm Thu Dec 07 11:53:44 2017 +0530 @@ -14095,7 +14095,7 @@ ;avx512 luma_vss code end ;------------------------------------------------------------------------------------------------------------- ;------------------------------------------------------------------------------------------------------------- -;avx512 luma_vpp code start +;avx512 luma_vpp and luma_vps code start ;------------------------------------------------------------------------------------------------------------- %macro PROCESS_LUMA_VERT_PP_16x8_AVX512 0 lea r5, [r0 + 4 * r1] @@ -14627,8 +14627,7 @@ %if ARCH_X86_64 FILTER_VER_PP_LUMA_48x64_AVX512 %endif - -%macro PROCESS_LUMA_VERT_PP_64x2_AVX512 0 +%macro PROCESS_LUMA_VERT_64x2_AVX512 1 lea r5, [r0 + 4 * r1] movu m1, [r0] movu m3, [r0 + r1] @@ -14695,7 +14694,7 @@ paddw m1, m13 paddw m2, m14 paddw m3, m15 - +%ifidn %1,pp pmulhrsw m0, m7 pmulhrsw m1, m7 pmulhrsw m2, m7 @@ -14705,20 +14704,36 @@ packuswb m2, m3 movu [r2], m0 movu [r2 + r3], m2 -%endmacro - +%else + psubw m0, m7 + psubw m1, m7 + psubw m2, m7 + psubw m3, m7 + + mova m12, m16 + mova m13, m17 + mova m14, m16 + mova m15, m17 + + vpermi2q m12, m0, m1 + vpermi2q m13, m0, m1 + vpermi2q m14, m2, m3 + vpermi2q m15, m2, m3 + + movu [r2], m12 + movu [r2 + mmsize], m13 + movu [r2 + r3], m14 + movu [r2 + r3 + mmsize], m15 +%endif +%endmacro ;----------------------------------------------------------------------------------------------------------------- ; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx) ;----------------------------------------------------------------------------------------------------------------- -%macro FILTER_VER_PP_LUMA_64xN_AVX512 1 +%macro FILTER_VERT_LUMA_64xN_AVX512 2 INIT_ZMM avx512 -cglobal interp_8tap_vert_pp_64x%1, 5, 8, 16 +cglobal interp_8tap_vert_%1_64x%2, 5, 8, 18 mov r4d, r4m shl r4d, 8 - lea r6, [3 * r1] - lea r7, [3 * r3] - sub r0, r6 - %ifdef PIC lea r5, [tab_LumaCoeffVer_32_avx512] mova m8, [r5 + r4] @@ -14731,25 +14746,41 @@ mova m10, [tab_LumaCoeffVer_32_avx512 + r4 + 2 * mmsize] mova m11, [tab_LumaCoeffVer_32_avx512 + r4 + 3 * mmsize] %endif - +%ifidn %1, pp vbroadcasti32x8 m7, [pw_512] -%rep %1/2 - 1 - PROCESS_LUMA_VERT_PP_64x2_AVX512 +%else + add r3d, r3d + vbroadcasti32x8 m7, [pw_2000] + mova m16, [interp4_vps_store1_avx512] + mova m17, [interp4_vps_store2_avx512] +%endif + + lea r6, [3 * r1] + sub r0, r6 + lea r7, [3 * r3] + +%rep %2/2 - 1 + PROCESS_LUMA_VERT_64x2_AVX512 %1 lea r0, [r0 + 2 * r1] lea r2, [r2 + 2 * r3] %endrep - PROCESS_LUMA_VERT_PP_64x2_AVX512 + PROCESS_LUMA_VERT_64x2_AVX512 %1 RET %endmacro %if ARCH_X86_64 -FILTER_VER_PP_LUMA_64xN_AVX512 16 -FILTER_VER_PP_LUMA_64xN_AVX512 32 -FILTER_VER_PP_LUMA_64xN_AVX512 48 -FILTER_VER_PP_LUMA_64xN_AVX512 64 -%endif -;------------------------------------------------------------------------------------------------------------- -;avx512 luma_vpp code end +FILTER_VERT_LUMA_64xN_AVX512 pp, 16 +FILTER_VERT_LUMA_64xN_AVX512 pp, 32 +FILTER_VERT_LUMA_64xN_AVX512 pp, 48 +FILTER_VERT_LUMA_64xN_AVX512 pp, 64 + +FILTER_VERT_LUMA_64xN_AVX512 ps, 16 +FILTER_VERT_LUMA_64xN_AVX512 ps, 32 +FILTER_VERT_LUMA_64xN_AVX512 ps, 48 +FILTER_VERT_LUMA_64xN_AVX512 ps, 64 +%endif +;------------------------------------------------------------------------------------------------------------- +;avx512 luma_vpp and luma_vps code end ;------------------------------------------------------------------------------------------------------------- ;------------------------------------------------------------------------------------------------------------- ;ipfilter_luma_avx512 code end _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel