flight 52776 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52776/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-freebsd10-amd64 15 guest-localmigrate.2 fail REGR. vs. 36764
test-amd64-i386-freebsd10-i3
flight 52702 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52702/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-credit2 13 guest-saverestore fail REGR. vs. 50329
test-amd64-amd64-xl-m
flight 52661 xen-4.3-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52661/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-freebsd10-amd64 16 guest-localmigrate/x10 fail REGR. vs. 36755
test-amd64-amd64-
flight 52652 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52652/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-freebsd10-amd64 13 guest-localmigrate fail REGR. vs. 50391
test-amd64-i386-xl-
From: "Edgar E. Iglesias"
The Stage2 input-size must match what the CPU uses because
the SMMU and the CPU share page-tables.
Test that the SMMU supports the P2M IPA bit size, use it if
supported or bail out if not.
Signed-off-by: Edgar E. Iglesias
---
xen/drivers/passthrough/arm/smmu.c | 10 +
From: "Edgar E. Iglesias"
Export p2m_ipa_bits holding the bit size of IPAs used in p2m tables.
Signed-off-by: Edgar E. Iglesias
---
xen/arch/arm/p2m.c| 5 +
xen/include/asm-arm/p2m.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
ind
From: "Edgar E. Iglesias"
This is needed to allow the paging setup to probe for
IPA bit sizes to be used in p2m tables prior to iommu setup.
Reviewed-by: Julien Grall
Signed-off-by: Edgar E. Iglesias
---
xen/arch/arm/setup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --gi
On Thu, Apr 30, 2015 at 04:07:27PM +0100, Julien Grall wrote:
> Hi Edgar,
>
> On 30/04/15 12:55, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > The Stage2 input-size must match what the CPU uses because
> > the SMMU and the CPU share page-tables.
> >
> > Assert that the SMMU sup
From: "Edgar E. Iglesias"
Hi,
This is a fix for the issue I'm seeing on ZynqMP with missmatched
setup of the SMMU and the shared p2m page-tables with the CPU.
This implementes a global p2m_ipa_bits cap for S2 input-size as
discussed in the previous RFC.
Best regards,
Edgar
Changelog:
v3 -> v4
On Thu, Apr 30, 2015 at 04:46:38PM -0500, Bjorn Helgaas wrote:
> On Thu, Apr 30, 2015 at 07:27:23PM +0200, Luis R. Rodriguez wrote:
> > On Thu, Apr 30, 2015 at 11:26:47AM -0500, Bjorn Helgaas wrote:
>
> > > I don't see users of either pcim_iomap_wc() or pcim_iomap_wc_regions() so
> > > far. Did I
flight 52651 xen-4.2-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52651/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-debianhvm-amd64 5 xen-install fail REGR. vs. 36512
test-amd64-i386-q
flight 52649 xen-4.5-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52649/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-armhf-armhf-xl-credit2 6 xen-boot fail REGR. vs. 50408
test-amd64-amd64-
On 04/30/2015 03:35 PM, Andy Lutomirski wrote:
On Thu, Apr 30, 2015 at 12:30 PM, Boris Ostrovsky
wrote:
On 04/30/2015 03:17 PM, Andy Lutomirski wrote:
On Thu, Apr 30, 2015 at 12:08 PM, Boris Ostrovsky
wrote:
Commit 61f01dd941ba ("x86_64, asm: Work around AMD SYSRET SS descriptor
attribute is
flight 52703 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52703/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-armhf-armhf-libvirt 11 guest-start fail REGR. vs. 50368
Tests which did not succe
On Thu, Apr 30, 2015 at 07:27:23PM +0200, Luis R. Rodriguez wrote:
> On Thu, Apr 30, 2015 at 11:26:47AM -0500, Bjorn Helgaas wrote:
> > I don't see users of either pcim_iomap_wc() or pcim_iomap_wc_regions() so
> > far. Did I miss them, or do you just expect them in the near future?
>
> The later
From: "Luis R. Rodriguez"
We are burrying direct access to MTRR code support on
x86 in order to take advantage of PAT. In the future we
also want to make the default behaviour of ioremap_nocache()
to use strong UC, use of mtrr_add() on those systems
would make write-combining void.
In order to h
From: "Luis R. Rodriguez"
We are burrying direct access to MTRR code support on
x86 in order to take advantage of PAT. In the future we
also want to make the default behaviour of ioremap_nocache()
to use strong UC, use of mtrr_add() on those systems
would make write-combining void.
In order to h
On Thu, Apr 30, 2015 at 12:30 PM, Boris Ostrovsky
wrote:
> On 04/30/2015 03:17 PM, Andy Lutomirski wrote:
>>
>> On Thu, Apr 30, 2015 at 12:08 PM, Boris Ostrovsky
>> wrote:
>>>
>>> Commit 61f01dd941ba ("x86_64, asm: Work around AMD SYSRET SS descriptor
>>> attribute issue") makes AMD processors se
On 04/30/2015 03:17 PM, Andy Lutomirski wrote:
On Thu, Apr 30, 2015 at 12:08 PM, Boris Ostrovsky
wrote:
Commit 61f01dd941ba ("x86_64, asm: Work around AMD SYSRET SS descriptor
attribute issue") makes AMD processors set SS to __KERNEL_DS in
__switch_to() to deal with cases when SS is NULL.
This
On Thu, Apr 30, 2015 at 12:08 PM, Boris Ostrovsky
wrote:
> Commit 61f01dd941ba ("x86_64, asm: Work around AMD SYSRET SS descriptor
> attribute issue") makes AMD processors set SS to __KERNEL_DS in
> __switch_to() to deal with cases when SS is NULL.
>
> This breaks Xen PV guests who do not want to
Commit 61f01dd941ba ("x86_64, asm: Work around AMD SYSRET SS descriptor
attribute issue") makes AMD processors set SS to __KERNEL_DS in
__switch_to() to deal with cases when SS is NULL.
This breaks Xen PV guests who do not want to load SS with__KERNEL_DS.
Since the problem that the commit is tryi
On 04/29/2015 02:27 PM, Linus Torvalds wrote:
On Wed, Apr 29, 2015 at 11:11 AM, Peter Zijlstra wrote:
On Fri, Apr 24, 2015 at 02:56:42PM -0400, Waiman Long wrote:
In the pv_scan_next() function, the slow cmpxchg atomic operation is
performed even if the other CPU is not even close to being hal
On 04/29/2015 02:11 PM, Peter Zijlstra wrote:
On Fri, Apr 24, 2015 at 02:56:42PM -0400, Waiman Long wrote:
In the pv_scan_next() function, the slow cmpxchg atomic operation is
performed even if the other CPU is not even close to being halted. This
extra cmpxchg can harm slowpath performance.
Th
Signed-off-by: Don Slutz
(cherry picked from commit b72adbe7510d0a30053d32334665ee887bec9e43)
---
trace-events | 7 +++
xen-hvm.c| 21 +
2 files changed, 28 insertions(+)
diff --git a/trace-events b/trace-events
index 30eba92..4666dad 100644
--- a/trace-events
+++ b/
On Fri, Mar 20, 2015 at 4:18 PM, Luis R. Rodriguez
wrote:
> The same area used for ioremap() is used for the MTRR area.
> Convert the driver from using the x86 specific MTRR code to
> the architecture agnostic arch_phys_wc_add(). arch_phys_wc_add()
> will avoid MTRR if write-combining is available
From: "Luis R. Rodriguez"
This allows drivers to take advantage of write-combining
when possible. The PCI specification does not allow for us
to automatically identify a memory region which needs
write-combining so drivers have to identify these areas
on their own. There is IORESOURCE_PREFETCH bu
On Thu, Apr 30, 2015 at 11:26:47AM -0500, Bjorn Helgaas wrote:
> [+cc linux-pci]
>
> Hi Luis,
>
> On Wed, Apr 29, 2015 at 02:36:09PM -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez"
> >
> > Now that we have pci_iomap_wc() add the respective devres helpers.
>
> I guess I'm still co
On Thu, Apr 30, 2015 at 10:03:18AM -0700, Andy Lutomirski wrote:
> On Thu, Apr 30, 2015 at 9:52 AM, Luis R. Rodriguez wrote:
> > On Thu, Apr 30, 2015 at 10:59:17AM -0500, Bjorn Helgaas wrote:
> >> [+cc linux-pci]
> >>
> >> Hi Luis,
> >>
> >> On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodrig
On Thu, Apr 30, 2015 at 9:52 AM, Luis R. Rodriguez wrote:
> On Thu, Apr 30, 2015 at 10:59:17AM -0500, Bjorn Helgaas wrote:
>> [+cc linux-pci]
>>
>> Hi Luis,
>>
>> On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodriguez wrote:
>> > From: "Luis R. Rodriguez"
>> >
>> > This allows drivers to tak
On Thu, 30 Apr 2015, Anthony PERARD wrote:
> On Wed, Apr 29, 2015 at 06:00:54PM +0100, Stefano Stabellini wrote:
> > Introduce a new command to run functional tests and unit tests.
> > Introduce a generic infrastrucutre to run tests on the local machine.
> > Add a library of common functions that c
Fabio Fantoni wrote:
> Il 29/04/2015 18:39, Jim Fehlig ha scritto:
>> dom0 and domU are both SLES12. Xen is fairly recent xen-unstable plus a
>> few libxl patches.
>>
>> Regards,
>> Jim
>>
>
> But the domU was without qxl driver installed?
No, it was installed:
linux-tyb8:~/ # dmesg | grep -i qx
On Thu, Apr 30, 2015 at 10:59:17AM -0500, Bjorn Helgaas wrote:
> [+cc linux-pci]
>
> Hi Luis,
>
> On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodriguez wrote:
> > From: "Luis R. Rodriguez"
> >
> > This allows drivers to take advantage of write-combining
> > when possible. Ideally we'd hav
On Thu, 30 Apr 2015, Anthony PERARD wrote:
> On Wed, Apr 29, 2015 at 06:00:56PM +0100, Stefano Stabellini wrote:
> > Introduce an error_echo function that prints to stderr.
> > Call error_echo or verbose_echo, instead of echo, when possible and
> > appropriate.
> > Redirect build and tests output t
On 04/30/2015 03:53 AM, Juergen Gross wrote:
> Paravirtualized spinlocks produce some overhead even if the kernel is
> running on bare metal. The main reason are the more complex locking
> and unlocking functions. Especially unlocking is no longer just one
> instruction but so complex that it is no
[+cc linux-pci]
Hi Luis,
On Wed, Apr 29, 2015 at 02:36:09PM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
>
> Now that we have pci_iomap_wc() add the respective devres helpers.
I guess I'm still confused about the relationship between pci_iomap_wc()
and arch_phys_wc_add().
Do yo
[+cc linux-pci]
Hi Luis,
On Wed, Apr 29, 2015 at 02:36:08PM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
>
> This allows drivers to take advantage of write-combining
> when possible. Ideally we'd have pci_read_bases() just
> peg an IORESOURCE_WC flag for us
This makes it sound
On 30/04/15 11:42, Roger Pau Monne wrote:
Since a PVH hardware domain has access to the physical hardware create a
custom more permissive IO bitmap. The permissions set on the bitmap are
populated based on the contents of the ioports rangeset.
Signed-off-by: Roger Pau Monné
Cc: Jan Beulich
Cc:
On 23/04/15 13:42, David Vrabel wrote:
> On 21/04/15 11:22, Jan Beulich wrote:
> On 21.04.15 at 12:11, wrote:
>>> We have analysed the affect of this series on interrupt latency (by
>>> measuring the duration of irq disable/enable regions) and there is no
>>> signficant impact.
>>>
>>> http://
add_sized(ptr, inc) adds inc to the value at ptr using only the correct
size of loads and stores for the type of *ptr. The add is /not/ atomic.
This is needed for ticket locks to ensure the increment of the head ticket
does not affect the tail ticket.
Signed-off-by: David Vrabel
---
xen/includ
Pack struct hvm_domain to reduce it by 8 bytes. Thus reducing the
size of struct domain by 8 bytes.
Signed-off-by: David Vrabel
---
xen/include/asm-x86/hvm/domain.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/xen/include/asm-x86/hvm/domain.h b/xen/include/
Now that all architecture use a common ticket lock implementation for
spinlocks, remove the architecture specific byte lock implementations.
Signed-off-by: David Vrabel
Reviewed-by: Tim Deegan
Acked-by: Jan Beulich
---
xen/arch/arm/README.LinuxPrimitives | 28 ---
xen/include/as
arch_fetch_and_add() atomically adds a value and returns the previous
value.
This generic arm implementation uses the GCC __sync_fetch_and_add()
builtin. This builtin resulted in suitable inlined asm for GCC 4.8.3
(arm64) and GCC 4.6.3 (arm32).
This is needed to implement ticket locks.
Signed-o
add_sized(ptr, inc) adds inc to the value at ptr using only the correct
size of loads and stores for the type of *ptr. The add is /not/ atomic.
This is needed for ticket locks to ensure the increment of the head ticket
does not affect the tail ticket.
Signed-off-by: David Vrabel
---
xen/includ
Replace the byte locks with ticket locks. Ticket locks are: a) fair;
and b) peform better when contented since they spin without an atomic
operation.
The lock is split into two ticket values: head and tail. A locker
acquires a ticket by (atomically) increasing tail and using the
previous tail va
arch_fetch_and_add() atomically adds a value and returns the previous
value.
This is needed to implement ticket locks.
Signed-off-by: David Vrabel
---
xen/include/asm-x86/system.h | 48 ++
1 file changed, 48 insertions(+)
diff --git a/xen/include/asm-x
Pack struct paging_domain to reduce it by 8 bytes. Thus reducing the
size of struct domain by 8 bytes.
Signed-off-by: David Vrabel
---
xen/include/asm-x86/domain.h |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/include/asm-x86/domain.h b/xen/include/asm-x86/domai
Use ticket locks for spin locks instead of the current byte locks.
Ticket locks are fair. This is an important property for hypervisor
locks.
Note that spin_lock_irq() and spin_lock_irqsave() now spin with irqs
disabled (previously, they would spin with irqs enabled if possible).
This is required
On 04/30/2015 09:21 AM, Xu, Quan wrote:
Stefan,
Sorry to reply so late to you. I try to make it compatible with Xen
vTPM by below patch
Against your serious of
patch(https://github.com/KevinOConnor/seabios/tree/tcg-testing ).
Also I have tested this patch, which is working.
Thanks.
On Wed, Apr 29, 2015 at 06:00:56PM +0100, Stefano Stabellini wrote:
> Introduce an error_echo function that prints to stderr.
> Call error_echo or verbose_echo, instead of echo, when possible and
> appropriate.
> Redirect build and tests output to /dev/null unless VERBOSE==1.
> Redirect apt-get and
At 14:28 +0100 on 30 Apr (1430404125), David Vrabel wrote:
> From: Malcolm Crossley
>
> Performance analysis of aggregate network throughput with many VMs
> shows that performance is signficantly limited by contention on the
> maptrack lock when obtaining/releasing maptrack handles from the free
Hi Edgar,
On 30/04/15 12:55, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> The Stage2 input-size must match what the CPU uses because
> the SMMU and the CPU share page-tables.
>
> Assert that the SMMU supports the P2M IPA bit size and use it.
>
> Signed-off-by: Edgar E. Iglesias
>
flight 52633 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52633/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-multivcpu 11 guest-start fail REGR. vs. 50405
test-amd64-amd64-xl-
Hi Edgar,
On 30/04/15 12:55, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Export p2m_ipa_bits holding the bit size of IPA addresses used
NIT: I think "addresses" is redundant here. IPA always has the word
"address" in it
> in p2m tables.
>
> Signed-off-by: Edgar E. Iglesias
> ---
On Wed, Apr 29, 2015 at 06:00:54PM +0100, Stefano Stabellini wrote:
> Introduce a new command to run functional tests and unit tests.
> Introduce a generic infrastrucutre to run tests on the local machine.
> Add a library of common functions that can be used by the test scripts
> to setup guest VMs
Hi,
What is the proper way to handle shared pages (either side - using
gntdev or gntalloc) regarding fork and possible exec later? The child
process do not need to access those pages in any way, but will map
different one(s), using newly opened FD to the gntdev/gntalloc device.
Should it unmap the
At 14:28 +0100 on 30 Apr (1430404124), David Vrabel wrote:
> +/*
> + * N.B.: while taking the left side maptrack spinlock prevents
> + * any mapping changes, the right side active entries could be
> + * changing while we are counting.
IIRC, the lX/rX variables are local/remote rat
Hi,
On 30/04/15 14:47, Stefano Stabellini wrote:
If the devid is not within this range, the ITS won't recognize the value
and
won't be able to send the interrupt.
So this is clearly not the right value.
>>>
>>> Sure, in that case the maximum value allowed by GITS_TYP
The current base directory /var/xen for domU dumps will be patched to
/var/lib/xen by most distros. Provide a configure option to avoid
patching the source.
If the option is not specified the default remains /var/xen/dump.
Please rerun autogen.sh after applying this patch.
Signed-off-by: Olaf He
On Thu, 30 Apr 2015, Vijay Kilari wrote:
> On Thu, Apr 30, 2015 at 3:45 PM, Stefano Stabellini
> wrote:
> > On Thu, 30 Apr 2015, Julien Grall wrote:
> >> Hi Stefano,
> >>
> >> On 30/04/2015 11:02, Stefano Stabellini wrote:
> >> > On Wed, 29 Apr 2015, Julien Grall wrote:
> >> > > On 29/04/15 17:30,
From: Malcolm Crossley
Performance analysis of aggregate network throughput with many VMs
shows that performance is signficantly limited by contention on the
maptrack lock when obtaining/releasing maptrack handles from the free
list.
Instead of a single free list use a per-VCPU list. This avoids
From: Christoph Egger
Split grant table lock into two separate locks. One to protect
maptrack state and change the other into a rwlock.
The rwlock is used to prevent readers from accessing inconsistent
grant table state such as current version, partially initialized
active table pages, etc.
Sig
The series makes the grant table locking more fine-grained and adds
per-VCPU maptrack free lists, which greatly improves scalability.
The series builds on the original series by Matt Wilson and Christoph
Egger from Amazon.
Performance results for aggregate intrahost network throughput
(between 20
From: Matt Wilson
This patch refactors grant table locking. It splits the previous
single spinlock per grant table into multiple locks. The heavily
modified components of the grant table (the maptrack state and the
active entries) are now protected by their own spinlocks. The
remaining elements o
> -Original Message-
> From: Stefan Berger [mailto:stef...@linux.vnet.ibm.com]
> Sent: Wednesday, April 29, 2015 7:18 PM
> To: Xu, Quan
> Cc: Kevin O'Connor; seab...@seabios.org; stefano.stabell...@eu.citrix.com;
> xen-devel@lists.xen.org; Daniel De Graaf; wei.l...@citrix.com
> Subject: R
On Thu, Apr 30, 2015 at 3:45 PM, Stefano Stabellini
wrote:
> On Thu, 30 Apr 2015, Julien Grall wrote:
>> Hi Stefano,
>>
>> On 30/04/2015 11:02, Stefano Stabellini wrote:
>> > On Wed, 29 Apr 2015, Julien Grall wrote:
>> > > On 29/04/15 17:30, Vijay Kilari wrote:
>> > > > On Wed, Apr 29, 2015 at 9:5
From: "Edgar E. Iglesias"
The Stage2 input-size must match what the CPU uses because
the SMMU and the CPU share page-tables.
Assert that the SMMU supports the P2M IPA bit size and use it.
Signed-off-by: Edgar E. Iglesias
---
xen/drivers/passthrough/arm/smmu.c | 5 +++--
1 file changed, 3 inse
From: "Edgar E. Iglesias"
Export p2m_ipa_bits holding the bit size of IPA addresses used
in p2m tables.
Signed-off-by: Edgar E. Iglesias
---
xen/arch/arm/p2m.c| 5 +
xen/include/asm-arm/p2m.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/
From: "Edgar E. Iglesias"
This is needed to allow the paging setup to probe for
IPA bit sizes to be used in p2m tables prior to iommu setup.
Reviewed-by: Julien Grall
Signed-off-by: Edgar E. Iglesias
---
xen/arch/arm/setup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Hi,
This is a fix for the issue I'm seeing on ZynqMP with missmatched
setup of the SMMU and the shared p2m page-tables with the CPU.
This implementes a global p2m_ipa_bits cap for S2 input-size as
discussed in the previous RFC.
Best regards,
Edgar
Changelog:
v2 -> v3
On 30/04/15 11:09, Tim Deegan wrote:
> At 00:56 +0100 on 30 Apr (1430355366), Jan Beulich wrote:
> David Vrabel 04/29/15 5:28 PM >>>
>>> On 29/04/15 00:15, Jan Beulich wrote:
>>> David Vrabel 04/28/15 6:16 PM >>>
> Are there any structures whose size you're particularly concerned abou
On Thu, Apr 30, 2015 at 10:39:19AM +0100, Julien Grall wrote:
> Hi Edgar,
>
> On 30/04/2015 07:06, Edgar E. Iglesias wrote:
> > val |= VTCR_T0SZ(0x18); /* 40 bit IPA */
> > val |= VTCR_SL0(0x1); /* P2M starts at first level */
> > #else /* CONFIG_ARM_64 */
> >@@ -1557,6 +1561,7 @@ void
flight 52629 xen-4.4-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52629/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-armhf-libvirt 5 libvirt-build fail REGR. vs. 50429
test-amd64-amd64-
Hi,
At 15:31 +0100 on 24 Apr (1429889471), Jan Beulich wrote:
> --- a/xen/arch/x86/mm/shadow/multi.c
> +++ b/xen/arch/x86/mm/shadow/multi.c
> @@ -1435,6 +1435,14 @@ void sh_install_xen_entries_in_l4(struct
> shadow_l4e_from_mfn(page_to_mfn(d->arch.perdomain_l3_pg),
>
At 16:19 +0800 on 24 Apr (1429892368), Kai Huang wrote:
> v2->v3:
>
> - Merged v2 patch 02 (document change) to patch 01 as a single patch, and
> changed new parameter description as suggested by Andrew.
> - changed vmx_vcpu_flush_pml_buffer to call mark_dirty for all logged GFNs,
> and
> cal
The decision whether the slowpath flag is to be cleared for
paravirtualized spinlocks is located in
__ticket_check_and_clear_slowpath() today.
Move that decision into arch_spin_lock() and add an unlikely attribute
to it to avoid calling a function in case the compiler chooses not to
inline __ticke
Paravirtualized spinlocks produce some overhead even if the kernel is
running on bare metal. The main reason are the more complex locking
and unlocking functions. Especially unlocking is no longer just one
instruction but so complex that it is no longer inlined.
This patch series addresses this is
There is no need any more for a special treatment of _raw_spin_unlock()
regarding inlining compared to the other spinlock functions. Just treat
it like all the other spinlock functions.
Remove selecting UNINLINE_SPIN_UNLOCK in case of PARAVIRT_SPINLOCKS.
Signed-off-by: Juergen Gross
---
arch/x8
To speed up paravirtualized spinlock handling when running on bare
metal introduce a new pvops function "spin_unlock". This is a simple
add instruction (possibly with lock prefix) when the kernel is running
on bare metal.
As the patched instruction includes a lock prefix in some
configurations ann
With the paravirtualized spinlock unlock function being a pvops
function paravirt_ticketlocks_enabled is no longer needed. Remove it.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/spinlock.h | 3 ---
arch/x86/kernel/kvm.c| 14 --
arch/x86/kernel/paravirt
To speed up paravirtualized spinlock handling when running on bare
metal introduce a new pvops function "clear_slowpath". This is a nop
when the kernel is running on bare metal.
As the clear_slowpath function is common for all users add a new
initialization function to set the pvops function point
For paravirtualized spinlocks setting the "slowpath" flag in
__ticket_enter_slowpath() is done via setting bit "0" in
lock->tickets.head instead of using a macro.
Change this by defining an appropriate macro.
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/spinlock.h | 3 ++-
arch/x
On Thu, 30 Apr 2015, Julien Grall wrote:
> On 30/04/2015 11:15, Stefano Stabellini wrote:
> > > As said earlier, the number of DevBits implemented by the ITS can be
> > > limited
> > > (see GITS_TYPER.Devbits).
> > >
> > > If the devid is not within this range, the ITS won't recognize the value
>
Since a PVH hardware domain has access to the physical hardware create a
custom more permissive IO bitmap. The permissions set on the bitmap are
populated based on the contents of the ioports rangeset.
Signed-off-by: Roger Pau Monné
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Boris Ostrovsky
Cc: Sur
Il 29/04/2015 18:39, Jim Fehlig ha scritto:
Fabio Fantoni wrote:
Il 29/04/2015 02:21, Andrew Cooper ha scritto:
On 28/04/15 23:17, Jim Fehlig wrote:
Jim Fehlig wrote:
wei.l...@citrix.com wrote:
Hi all
We are now three months into 4.6 development window. This is an
email to keep
track of all
On 30/04/2015 11:15, Stefano Stabellini wrote:
As said earlier, the number of DevBits implemented by the ITS can be limited
(see GITS_TYPER.Devbits).
If the devid is not within this range, the ITS won't recognize the value and
won't be able to send the interrupt.
So this is clearly not the ri
On Thu, 30 Apr 2015, Julien Grall wrote:
> Hi Stefano,
>
> On 30/04/2015 11:02, Stefano Stabellini wrote:
> > On Wed, 29 Apr 2015, Julien Grall wrote:
> > > On 29/04/15 17:30, Vijay Kilari wrote:
> > > > On Wed, Apr 29, 2015 at 9:56 PM, Vijay Kilari
> > > > wrote:
> > > > > On Wed, Apr 29, 2015 a
Hi Stefano,
On 30/04/2015 11:02, Stefano Stabellini wrote:
On Wed, 29 Apr 2015, Julien Grall wrote:
On 29/04/15 17:30, Vijay Kilari wrote:
On Wed, Apr 29, 2015 at 9:56 PM, Vijay Kilari wrote:
On Wed, Apr 29, 2015 at 7:05 PM, Julien Grall wrote:
On 29/04/15 12:56, Julien Grall wrote:
As th
At 00:56 +0100 on 30 Apr (1430355366), Jan Beulich wrote:
> >>> David Vrabel 04/29/15 5:28 PM >>>
> >On 29/04/15 00:15, Jan Beulich wrote:
> > David Vrabel 04/28/15 6:16 PM >>>
> >>> Are there any structures whose size you're particularly concerned about?
> >>
> >> No specific ones (but of c
On Wed, 29 Apr 2015, Pranavkumar Sawargaonkar wrote:
> In old X-Gene Storm firmware and DT, secure mode addresses have been
> mentioned in GICv2 node. In this case maintenance interrupt is used
> instead of EOI HW method.
>
> This patch checks the GIC Distributor Base Address to enable EOI quirk
>
On Wed, 29 Apr 2015, Julien Grall wrote:
> On 29/04/15 17:30, Vijay Kilari wrote:
> > On Wed, Apr 29, 2015 at 9:56 PM, Vijay Kilari
> > wrote:
> >> On Wed, Apr 29, 2015 at 7:05 PM, Julien Grall
> >> wrote:
> >>> On 29/04/15 12:56, Julien Grall wrote:
> As the 2 suggested approach don't see
Hi Edgar,
On 30/04/2015 07:06, Edgar E. Iglesias wrote:
val |= VTCR_T0SZ(0x18); /* 40 bit IPA */
val |= VTCR_SL0(0x1); /* P2M starts at first level */
#else /* CONFIG_ARM_64 */
@@ -1557,6 +1561,7 @@ void __init setup_virt_paging(void)
p2m_root_order = pa_range_info[pa_range]
Hi Edgar,
On 30/04/2015 07:06, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
This is needed to allow the paging setup to probe for
pfn bit sizes to be used in p2m tables prior to iommu setup.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Julien Grall
Regards,
--
Julien Grall
_
Hi Ian,
On 20/04/2015 13:16, Ian Campbell wrote:
This function iterates over a node's ranges property and calls a
callback for each region. For now it only supplies the MMIO range (in
terms of CPU addresses, i.e. already translated).
Signed-off-by: Ian Campbell
Reviewed-by: Julien Grall
Re
At 18:00 +0100 on 29 Apr (1430330400), David Vrabel wrote:
> On 29/04/15 17:56, Tim Deegan wrote:
> > At 16:36 +0100 on 29 Apr (1430325362), David Vrabel wrote:
> >> On 23/04/15 15:58, Jan Beulich wrote:
> >> On 23.04.15 at 16:43, wrote:
> At 14:54 +0100 on 23 Apr (1429800874), Jan Beulic
flight 52630 seabios real [real]
http://logs.test-lab.xenproject.org/osstest/logs/52630/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 36656
Tests which are failing i
On 2015/4/29 20:21, Al Viro wrote:
> On Wed, Apr 29, 2015 at 12:45:45PM +0100, Ian Jackson wrote:
>
>> The symptoms are that `umount' fails with EBUSY,
>
> [lizf: Backported to 3.4:
> - remove the changes to follow_link() as it doesn't call set_root()]
>
> looks dubious - I don't have -
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