-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index dccf101..ce90187 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++
redistributor. The maximum number of LPIs to be used can be adjusted with
the command line option "max_lpi_bits", which defaults to 20 bits,
covering about one million LPIs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@ke
-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c| 345 +++
xen/arch/arm/vgic-v3-its.c | 4 +
xen/include/asm-arm/domain.h | 3 +
xen/include/asm-arm/gic_v3_its.h | 13 ++
4 files changed, 365 insertions(+)
XEN_CONFIG_EXPERT=y on the make command line to see and use the option.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/Kconfig | 5 +++
xen/arch/arm/Makefile| 1 +
xen/arch/arm/gic-v3-its.c| 77
xen/ar
- add command line parameters on top of Kconfig options
- properly wait for an ITS to become quiescient before enabling it
- handle host ITS command queue errors
- actually wait for host ITS command completion (READR==WRITER)
- fix ARM32 compilation
- various patch splits and reorderings
Andre
gic_ops and a function to
retrieve the (cached) priority value of an LPI and a vgic_ops.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v2.c| 7 +
xen/arch/arm/gic-v3-lpi.c| 56
xen/arch/arm/gi
or pending table address while a redistributor
is live and also to protect the non-atomic vgic_reg64_extract() function
on the MMIO read side.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3.c | 158 +++
xen/inclu
The INT command sets a given LPI identified by a DeviceID/EventID pair
as pending and thus triggers it to be injected.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
missed this during an earlier
INVALL call (which only checks mapped LPIs).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c| 74 ++
xen/arch/arm/gic-v3-lpi.c| 18
xen/arch/arm/vgic-v3-its.c
to be on the safe side.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic.c | 23 +++
xen/arch/arm/vgic.c | 4
2 files changed, 27 insertions(+)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index da19130..44c34b1 100644
--- a/xen/ar
://patchwork.kernel.org/patch/8177251
Signed-off-by: Vijaya Kumar K <vijaya.ku...@caviumnetworks.com>
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic.c| 47 ++
xen/include/asm-arm/vgic.h | 3 +++
2 files changed, 50 inserti
This introduces the ITS command handler for the CLEAR command, which
clears the pending state of an LPI.
This removes a not-yet injected, but already queued IRQ from a VCPU.
As read_itte() is now eventually used, we add the static keyword.
Signed-off-by: Andre Przywara <andre.przyw...@arm.
processor number
in the GICR_TYPE register.
Advertise 24 bits worth of LPIs to the guest.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3.c | 59 +-
1 file changed, 54 insertions(+), 5 deletions(-)
diff --git a/x
Instead of directly manipulating the tables in memory, an ITS driver
sends commands via a ring buffer in normal system memory to the ITS h/w
to create or alter the LPI mappings.
Allocate memory for that buffer and tell the ITS about it to be able
to send ITS commands.
Signed-off-by: Andre
-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v2.c | 8
xen/arch/arm/vgic-v3.c | 23 +++
xen/arch/arm/vgic.c | 2 ++
xen/include/asm-arm/domain.h | 2 ++
xen/include/asm-arm/vgic.h | 2 ++
5 files changed, 37 inse
for mapping one collection to each host CPU.
As an ITS might choose between *two* ways of addressing a redistributor,
we store both the MMIO base address as well as the processor number in
a per-CPU variable to give each ITS what it wants.
Signed-off-by: Andre Przywara <andre.przyw...@arm.
The DISCARD command drops the connection between a DeviceID/EventID
and an LPI/collection pair.
We mark the respective structure entries as not allocated and make
sure that any queued IRQs are removed.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.
When creating the device tree for a domain using an emulated GICv3,
we will later need to add the respective ITS subnodes as well.
Prepare a stub function to be later filled with the actual code.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3.c
For LPIs we later want to dynamically allocate struct pending_irqs.
Let's export the vgic_init_pending_irq() to be able to reuse it.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic.c| 2 +-
xen/include/asm-arm/vgic.h | 1 +
2 files changed, 2 insertions
command and create
the required tables.
We simply use our existing guest memory access function to find the
right ITT entry and store the mapping there.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 59 +++
Create a new file to hold the emulation code for the ITS widget.
This just holds the data structure and a init and free function for now.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/Makefile| 1 +
xen/arch/arm/vgic-v3-its.c
Emulate the memory mapped ITS registers and provide a stub to introduce
the ITS command handling framework (but without actually emulating any
commands at this time).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c
this by storing the pending bit in struct
pending_irq, which is associated with mapped LPIs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-lpi.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/
Map the registers frame for each host ITS and populate the host ITS
structure with some parameters describing the size of certain properties
like the number of bits for device IDs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Julien Grall <julien.gr...@arm.com&
Hi,
On 07/04/17 14:47, Julien Grall wrote:
>
>
> On 07/04/17 14:45, Julien Grall wrote:
>>
>>
>> On 07/04/17 14:46, Andre Przywara wrote:
>>> Hi,
>>>
>>> On 07/04/17 14:41, Julien Grall wrote:
>>>> Hi Andre,
>>>&
Hi,
On 07/04/17 14:41, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 00:19, Andre Przywara wrote:
>> Dom0 expects all ITSes in the system to be propagated to be able to
>> use MSIs.
>> Create Dom0 DT nodes for each hardware ITS, keeping the register frame
>>
Hi,
On 07/04/17 14:07, Julien Grall wrote:
>
>
> On 06/04/17 00:19, Andre Przywara wrote:
>> +vgic_init_pending_irq(pirq, intid);
>> +
>> +/*
>> + * Now read the guest's property table to initialize our cached
>> state.
>> + * It can
Hi,
On 06/04/17 00:58, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> If a guest disables an LPI, we do not forward this to the associated
>> host LPI to avoid queueing commands to the host ITS command queue.
>> So it may happen that an LPI fires nev
Hi,
On 06/04/17 00:26, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> Parse the GIC subnodes in the device tree to find every ITS MSI controller
>> the hardware offers. Store that information in a list to both propagate
>> all of them later to Dom0
Hi Stefano,
thanks for spending your brain cells on this nasty code.
...
On 06/04/17 00:45, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> Upon receiving an LPI on the host, we need to find the right VCPU and
>> virtual IRQ number to get this IRQ injec
Hi,
On 06/04/17 16:34, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 00:19, Andre Przywara wrote:
>> The ITS uses device IDs to map LPIs to a device. Dom0 will later use
>> those IDs, which we directly pass on to the host.
>> For this we have to map each device that
Hi,
On 06/04/17 15:44, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 00:18, Andre Przywara wrote:
>> diff --git a/xen/include/asm-arm/gic_v3_its.h
>> b/xen/include/asm-arm/gic_v3_its.h
>> index 295eb22..6e51b98 100644
>> --- a/xen/include/asm-arm/gic_v3_i
Hi,
On 06/04/17 13:39, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 00:26, Stefano Stabellini wrote:
>> On Thu, 6 Apr 2017, Andre Przywara wrote:
>>> diff --git a/xen/include/asm-arm/gic_v3_its.h
>>> b/xen/include/asm-arm/gic_v3_its.h
>>> new f
Hi,
On 06/04/17 13:58, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 00:18, Andre Przywara wrote:
>> +static unsigned int max_lpi_bits = 20;
>> +integer_param("max_lpi_bits", max_lpi_bits);
>> +
>> +int gicv3_lpi_init_host_lpis(unsigned int host_l
Hi,
On 06/04/17 12:24, Julien Grall wrote:
> Hi Andre,
>
> On 06/04/17 12:25, Andre Przywara wrote:
>> On 06/04/17 00:55, Stefano Stabellini wrote:
>>> On Thu, 6 Apr 2017, Andre Przywara wrote:
>>>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.
Hi,
On 06/04/17 00:55, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> Allow a guest to provide the address and size for the memory regions
>> it has reserved for the GICv3 pending and property tables.
>> We sanitise the various fields of the res
Hi,
On 06/04/17 00:37, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> The number of LPIs on a host can be potentially huge (millions),
>> although in practise will be mostly reasonable. So prematurely allocating
>> an array of struct ir
Hi,
On 06/04/17 02:04, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> To let a guest know about the availability of virtual LPIs, set the
>> respective bits in the virtual GIC registers and let a guest control
>> the LPI enable bit.
>> Onl
Hi,
On 06/04/17 01:47, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> The MOVI command moves the interrupt affinity from one redistributor
>> (read: VCPU) to another.
>> For now migration of "live" LPIs is not yet implemented, but w
s for the code you are modifying.
>>
>> On 06/04/17 00:25, Stefano Stabellini wrote:
>>> On Thu, 6 Apr 2017, Andre Przywara wrote:
>>>> To safely handle 64-bit registers even on 32-bit systems, introduce
>>>> a GENMASK_ULL variant (lifted
Hi Stefano,
On 06/04/17 01:21, Stefano Stabellini wrote:
> On Thu, 6 Apr 2017, Andre Przywara wrote:
>> Emulate the memory mapped ITS registers and provide a stub to introduce
>> the ITS command handling framework (but without actually emulating any
>> commands at this ti
The DISCARD command drops the connection between a DeviceID/EventID
and an LPI/collection pair.
We mark the respective structure entries as not allocated and make
sure that any queued IRQs are removed.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.
-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c| 263 +++
xen/arch/arm/vgic-v3-its.c | 3 +
xen/include/asm-arm/domain.h | 3 +
xen/include/asm-arm/gic_v3_its.h | 13 ++
4 files changed, 282 insertions(+)
Now that the host part of the ITS code is in place, we can enable the
ITS and also LPIs on each redistributor to get the show rolling.
At this point there would be no LPIs mapped, as guests don't know about
the ITS yet.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/a
of an LPI and a vgic_ops.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v2.c| 7 +
xen/arch/arm/gic-v3-lpi.c| 56
xen/arch/arm/gic-v3.c| 1 +
xen/arch/arm/gic.c | 8 +-
xe
the virtual pending bit if an LPI gets enabled.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 96 ++
1 file changed, 96 insertions(+)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
This introduces the ITS command handler for the CLEAR command, which
clears the pending state of an LPI.
This removes a not-yet injected, but already queued IRQ from a VCPU.
As read_itte() is now eventually used, we add the static keyword.
Signed-off-by: Andre Przywara <andre.przyw...@arm.
again.
We advertise 24 bits worth of LPIs on the guest side, using the full
32 bits seems to trigger a Linux bug (to be investigated).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 46
xen/arch/arm/vgi
for mapping one collection to each host CPU.
As an ITS might choose between *two* ways of addressing a redistributor,
we store both the MMIO base address as well as the processor number in
a per-CPU variable to give each ITS what it wants.
Signed-off-by: Andre Przywara <andre.przyw...@arm.
Create a new file to hold the emulation code for the ITS widget.
This just holds the data structure and a init and free function for now.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/Makefile| 1 +
xen/arch/arm/vgic-v3-its.c
command and create
the required tables.
We simply use our existing guest memory access function to find the
right ITT entry and store the mapping there.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 59 +++
, since we can't easily protect those ITTs
from being altered by the guest.
To allow compiling without warnings, we declare two functions as
non-static for the moment, which two later patches will fix.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic.c | 2
Map the registers frame for each host ITS and populate the host ITS
structure with some parameters describing the size of certain properties
like the number of bits for device IDs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c
re enabling it
- handle host ITS command queue errors
- actually wait for host ITS command completion (READR==WRITER)
- fix ARM32 compilation
- various patch splits and reorderings
*** BLURB HERE ***
Andre Przywara (30):
bitops: add GENMASK_ULL
bitops: add BIT_ULL variant
ARM: GICv3 ITS: parse
for the ITS to use.
Allocate the required memory and hand it over to the ITS.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
xen/arch/arm/gic-v3-its.c| 132 +++
xen/inc
this by storing the pending bit in struct
pending_irq, which is assiociated with mapped LPIs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-lpi.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/gic-v3-l
store the VCPU ID in the pending_irq
struct as well.
This exports the vgic_init_pending_irq() function to be able to
initialize a new struct pending_irq.
As write_itte() is now eventually used, we can now add the static tag.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/a
The MAPC command associates a given collection ID with a given
redistributor, thus mapping collections to VCPUs.
We just store the vcpu_id in the collection table for that.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.
To safely handle 64-bit registers even on 32-bit systems, introduce
a GENMASK_ULL variant (lifted from Linux).
This adds a BITS_PER_LONG_LONG define as well.
Also fix a bug in the comment for the existing GENMASK variant.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/inclu
Dom0 expects all ITSes in the system to be propagated to be able to
use MSIs.
Create Dom0 DT nodes for each hardware ITS, keeping the register frame
address the same, as the doorbell address that the Dom0 drivers program
into the BARs has to match the hardware.
Signed-off-by: Andre Przywara
.
This patch introduces functions to initialize these tables and to
create, lookup and destroy entries for a given LPI.
By using the naturally atomic access guarantee the native uint64_t data
type gives us, we allocate and access LPI information in a way that does
not require a lock.
Signed-off-by: Andre
-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v2.c | 8
xen/arch/arm/vgic-v3.c | 22 ++
xen/arch/arm/vgic.c | 2 ++
xen/include/asm-arm/domain.h | 2 ++
xen/include/asm-arm/vgic.h | 2 ++
5 files changed, 36 inse
Emulate the memory mapped ITS registers and provide a stub to introduce
the ITS command handling framework (but without actually emulating any
commands at this time).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c
redistributor. The maximum number of LPIs to be used can be adjusted with
the command line option "max_lpi_bits", which defaults to 20 bits,
covering about one million LPIs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
docs/misc/xen-command-line.markdown | 9
-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index 0d4b20d..9684b3a 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++
The INT command sets a given LPI identified by a DeviceID/EventID pair
as pending and thus triggers it to be injected.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
processor number
in the GICR_TYPE register.
Advertise 24 bits worth of LPIs to the guest.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3.c | 46 +-
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/xen/
To safely handle 64-bit registers even on 32-bit systems, introduce
a BIT_ULL variant (lifted from Linux).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/include/asm-arm/bitops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/include/asm-arm/bitops.h b/xen/inclu
XEN_CONFIG_EXPERT=y on the make command line to see and use the option.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/Kconfig | 5 +++
xen/arch/arm/Makefile| 1 +
xen/arch/arm/gic-v3-its.c| 77
xen/ar
The MOVI command moves the interrupt affinity from one redistributor
(read: VCPU) to another.
For now migration of "live" LPIs is not yet implemented, but we store
the changed affinity in the host LPI structure and in our virtual ITTE.
Signed-off-by: Andre Przywara <andre.prz
Instead of directly manipulating the tables in memory, an ITS driver
sends commands via a ring buffer in normal system memory to the ITS h/w
to create or alter the LPI mappings.
Allocate memory for that buffer and tell the ITS about it to be able
to send ITS commands.
Signed-off-by: Andre
to read and write from and to guest memory,
to be later able to access the tables located there.
This vgic_access_guest_memory() function has been written by Vijaya Kumar
as part of an earlier series.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3.c
Hi,
On 04/04/17 20:02, Stefano Stabellini wrote:
> Also CC'ing Andre that I think has a pine64.
>
> On Tue, 4 Apr 2017, Stefano Stabellini wrote:
>> On Sat, 1 Apr 2017, bharat gohil wrote:
>>> Hello
>>
>> Hello Bharat, thanks for your email.
>>
>>
>>> I am trying to boot xen(debug build) on
Hi,
On 04/04/17 12:49, Julien Grall wrote:
>
>
> On 03/04/17 15:18, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 24/03/17 12:03, Julien Grall wrote:
>>>> +/* We may have mapped more host LPIs than the guest actually
>>>> asked
Hi,
On 03/04/17 21:41, Julien Grall wrote:
>
>
> On 04/03/2017 09:08 PM, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 22/03/17 17:29, Julien Grall wrote:
>>>> +int gicv3_its_map_guest_device(struct domain *d,
>>>> +
Parse the DT GIC subnodes to find every ITS MSI controller the hardware
offers. Store that information in a list to both propagate all of them
later to Dom0, but also to be able to iterate over all ITSes.
This introduces an ITS Kconfig option.
Signed-off-by: Andre Przywara <andre.przyw...@arm.
for mapping one collection to each host CPU.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c | 181 ++
xen/arch/arm/gic-v3-lpi.c | 28 ++
xen/arch/arm/gic-v3.c | 26 +-
xen/include/a
For each hardware ITS create and initialize a virtual ITS for Dom0.
We use the same memory mapped address to keep the doorbell working.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 32
xen/arch/arm/vgi
the virtual pending bit if an LPI gets enabled.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
The MOVI command moves the interrupt affinity from one redistributor
(read: VCPU) to another.
For now migration of "live" LPIs is not yet implemented, but we store
the changed affinity in the host LPI structure and in our virtual ITTE.
Signed-off-by: Andre Przywara <andre.prz
-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-lpi.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
index ad89863..a86fcf5 100644
--- a/xen/arch/arm/gic-v3-lpi.c
+++ b/xe
-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 46 ++
1 file changed, 46 insertions(+)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index 920c437..35a0730 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++
v3 controllers
- add command line parameters on top of Kconfig options
- properly wait for an ITS to become quiescient before enabling it
- handle host ITS command queue errors
- actually wait for host ITS command completion (READR==WRITER)
- fix ARM32 compilation
- various patch splits and reorde
, we can now add the static tag.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c| 70
xen/arch/arm/gic-v3-lpi.c| 18 +++
xen/arch/arm/vgic-v3-its.c | 36 +++--
xen/ar
Create a new file to hold the emulation code for the ITS widget.
For now we emulate the memory mapped ITS registers and provide a stub
to introduce the ITS command handling framework (but without actually
emulating any commands at this time).
Signed-off-by: Andre Przywara <andre.przyw...@arm.
The DISCARD command drops the connection between a DeviceID/EventID
and an LPI/collection pair.
We mark the respective structure entries as not allocated and make
sure that any queued IRQs are removed.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.
-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-lpi.c | 42 ++
xen/arch/arm/gic.c | 8 +++-
xen/arch/arm/vgic-v3.c | 11 +++
xen/arch/arm/vgic.c| 9 -
xen/include/asm-arm/irq.h | 2 ++
xen/i
Instead of directly manipulating the tables in memory, an ITS driver
sends commands via a ring buffer in normal system memory to the ITS h/w
to create or alter the LPI mappings.
Allocate memory for that buffer and tell the ITS about it to be able
to send ITS commands.
Signed-off-by: Andre
care of checking for a NULL pointer in the VCPU exit path,
should an LPI have been removed from the tree for any reason.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic.c | 12
xen/arch/arm/vgic-v3.c | 21 +
xen/ar
redistributor. The maximum number of LPIs to be used can be adjusted with
the command line option "max_lpi_bits", which defaults to 20 bits,
covering about one million LPIs.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
docs/misc/xen-command-line.markdown | 9
for the ITS to use.
Allocate the required memory and hand it to the ITS.
The maximum number of devices can be limited to a compile-time variable.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c| 132 +++
xen/i
Now that the host part of the ITS code is in place, we can enable the
ITS and also LPIs on each redistributor to get the show rolling.
At this point there would be no LPIs mapped, as guests don't know about
the ITS yet.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/a
The MAPC command associates a given collection ID with a given
redistributor, thus mapping collections to VCPUs.
We just store the vcpu_id in the collection table for that.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.
The INT command sets a given LPI identified by a DeviceID/EventID pair
as pending and thus triggers it to be injected.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/vgic-v3-its.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
.
This patch introduces functions to initialize these tables and to
create, lookup and destroy entries for a given LPI.
By using the naturally atomic access guarantee the native uint64_t data
type gives us, we allocate and access LPI information in a way that does
not require a lock.
Signed-off-by: Andre
-off-by: Andre Przywara <andre.przyw...@arm.com>
---
xen/arch/arm/gic-v3-its.c| 266 +++
xen/arch/arm/vgic-v3.c | 4 +
xen/include/asm-arm/domain.h | 3 +
xen/include/asm-arm/gic_v3_its.h | 17 +++
4 files changed, 290 insertions(+)
advertised by hardware.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
docs/misc/xen-command-line.markdown | 9
xen/arch/arm/gic-v3-its.c | 38
xen/arch/arm/gic-v3.c | 5 +
xen/include/asm-arm/gic_v3_its.h
To let a guest know about the availability of virtual LPIs, set the
respective bits in the virtual GIC registers and let a guest control
the LPI enable bit.
Only report the LPI capability if the host has initialized at least
one ITS.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
--
command and create
the required tables.
We don't map the device tables permanently, as their alignment
requirement is only 256 Bytes, thus making mapping of several tables
complicated. Instead we map the device tables on demand when we need
them later.
Signed-off-by: Andre Przywara <andre.pr
Dom0 expects all ITSes in the system to be propagated to be able to
use MSIs.
Create Dom0 DT nodes for each hardware ITS, keeping the register frame
address the same, as the doorbell address that the Dom0 drivers program
into the BARs has to match the hardware.
Signed-off-by: Andre Przywara
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