er-manual-325462.pdf.
Huaitong Han (3):
x86/hvm: pkeys, add pkeys support for guest_walk_tables
x86/hvm: pkeys, add xstate support for pkeys
x86/hvm: pkeys, add pkeys support for cpuid handling
tools/libxc/xc_cpufeature.h | 3 +++
tools/libxc/xc_cpuid_x86.c| 6 +++--
xe
X86_FEATURE_XSAVE, it is fixed too.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
Acked-by: Wei Liu <wei.l...@citrix.com>
---
Changes in v9:
*Clear X86_FEATURE_OSPKE and X86_FEATURE_OSXSAVE when the condition is not
satisfied.
Chan
The XSAVE feature set can operate on PKRU state only if the feature set is
enabled (CR4.OSXSAVE = 1) and has been configured to manage PKRU state
(XCR0[9] = 1). And XCR0.PKRU is disabled on PV mode without PKU feature
enabled.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Kevin Tian <kevin
X86_FEATURE_XSAVE, it is fixed too.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
Changes in v9:
*Clear X86_FEATURE_OSPKE and X86_FEATURE_OSXSAVE when the condition is not
satisfied.
Changes in v7:
*Rebase in the latest tree.
*Add a comment for cpu_has_xsave adjustment.
*Adjust inden
Protection Keys can be found at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
George Dunlap (1):
xen/mm: Clean up pfec handling in gva_to_gfn
Huaitong Han (4):
x86/hvm: pkeys, disable pke
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
---
Changes in v9:
*Renam
from gva_to_gfn.
(The PFEC_insn_fetch flag should only be passed to the guest if either NX or
SMEP is enabled. See Intel 64 Developer's Manual, Volume 3, Chapter Paging,
PAGE-FAULT EXCEPTIONS)
Signed-off-by: George Dunlap <george.dun...@citrix.com>
Signed-off-by: Huaitong Han <huaitong@intel.c
The XSAVE feature set can operate on PKRU state only if the feature set is
enabled (CR4.OSXSAVE = 1) and has been configured to manage PKRU state
(XCR0[9] = 1). And XCR0.PKRU is disabled on PV mode without PKU feature
enabled.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
The XSAVE feature set can operate on PKRU state only if the feature set is
enabled (CR4.OSXSAVE = 1) and has been configured to manage PKRU state
(XCR0[9] = 1). And XCR0.PKRU is disabled on PV mode without PKU feature
enabled.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Kevin Tian <kevin
X86_FEATURE_XSAVE, it is fixed too.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
---
Changes in v9:
*Clear X86_FEATURE_OSPKE and X86_FEATURE_OSXSAVE when the condition is not
satisfied.
Changes in v7:
*Rebase in the latest tree.
*A
ed as protection key violations.
The specification of Protection Keys can be found at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
George Dunlap (1):
xen/mm: Clean up pfec handling in gva_to_gfn
Hua
from gva_to_gfn.
(The PFEC_insn_fetch flag should only be passed to the guest if either NX or
SMEP is enabled. See Intel 64 Developer's Manual, Volume 3, Chapter Paging,
PAGE-FAULT EXCEPTIONS)
Signed-off-by: George Dunlap <george.dun...@citrix.com>
Signed-off-by: Huaitong Han <huaitong@intel.c
from gva_to_gfn.
(The PFEC_insn_fetch flag should only be passed to the guest if either NX or
SMEP is enabled. See Intel 64 Developer's Manual, Volume 3, Chapter Paging,
PAGE-FAULT EXCEPTIONS)
Signed-off-by: George Dunlap <george.dun...@citrix.com>
Signed-off-by: Huaitong Han <huaitong@intel.c
The XSAVE feature set can operate on PKRU state only if the feature set is
enabled (CR4.OSXSAVE = 1) and has been configured to manage PKRU state
(XCR0[9] = 1). And XCR0.PKRU is disabled on PV mode without PKU feature
enabled.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
s-software-developer-manual-325462.pdf.
George Dunlap (1):
xen/mm: Clean up pfec handling in gva_to_gfn
Huaitong Han (4):
x86/hvm: pkeys, disable pkeys for guests in non-paging mode
x86/hvm: pkeys, add pkeys support for guest_walk_tables
x86/hvm: pkeys, add xstate support for pkeys
x86/h
X86_FEATURE_XSAVE, it is fixed too.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
Changes in v7:
*Rebase in the latest tree.
*Add a comment for cpu_has_xsave adjustment.
*Adjust indentation.
tools/libxc/xc_cpufeature.h | 3 +++
tools/libxc/xc_cpuid_x86.c | 6 --
xen/arch/x
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
Changes in v8:
*Abstract out _write_cr4.
Changes in v7:
*Add static for pkey
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
Changes in v7:
no changes.
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han
nlap <george.dun...@citrix.com>
Signed-off-by: Huaitong Han <huaitong@intel.com>
Acked-by: Jan Beulich <jbeul...@suse.com>
---
xen/arch/x86/hvm/hvm.c | 8 ++--
xen/arch/x86/mm/hap/guest_walk.c | 10 +-
xen/arch/x86/mm/shadow/multi.c | 6 ++
3
without PKU feature
enabled.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
xen/arch/x86/xstate.c| 4
xen/include/asm-x86/xstate.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/xen/arch/
is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/mm/guest_walk.c | 54 +++
xen/arch/x86/mm/hap/guest_walk.c | 3 +++
xen/include/a
.PKE.
X86_FEATURE_OSXSAVE depends on guest X86_FEATURE_XSAVE, but cpu_has_xsave
function reflects hypervisor X86_FEATURE_XSAVE, it is fixed too.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
tools/libxc/xc_cpufeature.h | 3 +++
tools/libxc/xc_cpuid_x86.c | 6 --
xen/arch/x
ndling in gva_to_gfn
Huaitong Han (4):
x86/hvm: pkeys, disable pkeys for guests in non-paging mode
x86/hvm: pkeys, add pkeys support for guest_walk_tables
x86/hvm: pkeys, add xstate support for pkeys
x86/hvm: pkeys, add pkeys support for cpuid handling
tools/libxc/xc_cpufeature.h |
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/mm/guest_walk.c | 53 +++
xe
be passed to the guest if either NX or
SMEP is enabled. See Intel 64 Developer's Manual, Volume 3, Section 4.7.)
Signed-off-by: George Dunlap <george.dun...@citrix.com>
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/hvm/hvm.c | 8 ++--
xen/arch/x86/mm
The XSAVE feature set can operate on PKRU state only if the feature set is
enabled (CR4.OSXSAVE = 1) and has been configured to manage PKRU state
(XCR0[9] = 1). And XCR0.PKRU is disabled on PV mode without PKU feature
enabled.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
chitectures-software-developer-manual-325462.pdf.
Huaitong Han (5):
x86/hvm: pkeys, disable pkeys for guests in non-paging mode
x86/hvm: pkeys, add pkeys support for guest_walk_tables
x86/hvm: pkeys, add xstate support for pkeys
xen/mm: Clean up pfec handling in gva_to_gfn
x86/hvm: pkeys, add pke
This patch adds pkeys support for cpuid handing.
Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is
CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
tools/libxc/xc_cpufeature.h | 2 ++
tools
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (6):
x86/hvm: pkeys, add the flag to enable Memory Protection Keys
x86/hvm: pkeys, add pkeys support when setting CR4
x86/hvm: pkeys, disable pkeys for guests in non-paging mode
x86/hvm: pkeys, add pkeys support
CR4.PKE(bit 22) enables support for the RDPKRU/WRPKRU instructions to access
PKRU and
the protection keys check (a page fault trigger).
This patch adds X86_CR4_PKE to hvm_cr4_guest_reserved_bits so that CR4 check
works
before setting.
Signed-off-by: Huaitong Han <huaitong@intel.
This patch adds pkeys support for cpuid handing.
Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is
CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
tools/libxc/xc_cpufeature.h | 2 ++
tools
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
This patch adds the flag("pku") to enable Memory Protection Keys, and updates
the markdown.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
docs/misc/xen-command-line.markdown | 10 ++
xen
This patch adds xstate support for pkeys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
xen/arch/x86/xstate.c| 3 ++-
xen/include/asm-x86/xstate.h | 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/mm/guest_walk.c | 64 +++
xen/arch/
/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (6):
x86/hvm: pkeys, add the flag to enable Memory Protection Keys
x86/hvm: pkeys, add pkeys support when setting CR4
x86/hvm: pkeys, disable pkeys for guests in non-paging mode
x86/hvm: pkeys, add
.
5.The access is to a user page.
6.PKRU.AD=1
or The access is a data write and PKRU.WD=1
and either CR0.WP=1 or it is a user access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/mm/guest_walk.c | 65 +++
xen/arch/
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
This patch adds the flag to enable Memory Protection Keys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
docs/misc/xen-command-line.markdown | 10 ++
xen/arch/x86/cpu/common.c | 10 +-
xen/inc
This patch adds pkeys support when setting CR4.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
xen/arch/x86/hvm/hvm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/
This patch adds xstate support for pkeys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
xen/include/asm-x86/xstate.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/xen/include/asm-x86/xstate.h b
This patch adds pkeys support for cpuid handing.
Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is
CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
tools/libxc/xc_cpufeature.h | 2 ++
tools
The check needs to be against the xsave header in the area, rather than
Xen's maximum xfeature_mask. A guest might easily have a smaller xcr0
than the maximum Xen is willing to allow, causing the pointer below to
be bogus.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/ar
.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/xstate.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c
index b65da38..4e87ab3 100644
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -
This patch adds xstate support for pkeys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/xstate.c| 7 +--
xen/include/asm-x86/xstate.h | 4 +++-
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c
at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (9):
x86/hvm: pkeys, add the flag to enable Memory Protection Keys
x86/hvm: pkeys, add pkeys support when setting CR4
x86/hvm
This patch adds pkeys support for gva2gfn funcitons.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/hvm/hvm.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 59916ed..b88f381
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
This patch adds functions to get pkeys value from PTE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/include/asm-x86/guest_pt.h| 7 +++
xen/include/asm-x86/page.h| 5 +
xen/include/asm-x86/x86_64/page.h | 12
3 files changed, 24 inse
This patch adds the flag to enable Memory Protection Keys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
docs/misc/xen-command-line.markdown | 21 +
xen/arch/x86/cpu/common.c | 10 +++
This patch adds functions to support PKRU access.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/include/asm-x86/processor.h | 20
1 file changed, 20 insertions(+)
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index 3
This patch adds pkeys support when setting CR4.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
---
xen/arch/x86/hvm/hvm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/
This patch adds pkeys support for cpuid handing.
Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is
CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
tools/libxc/xc_cpufeature.h | 2 ++
tools
This patch adds pkeys support for guest_walk_tables.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/i387.c | 2 +-
xen/arch/x86/mm/guest_walk.c | 73 +++
xen/include/asm-x86/hvm/hvm.h | 2 ++
xen/include/asm-x86/
as protection key violations.
The specification of Protection Keys can be found at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (9):
x86/hvm: pkeys, add pkeys support for cpuid
This patch adds xstate support for pkeys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/xstate.c| 18 ++
xen/include/asm-x86/xstate.h | 5 -
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/xstate.c b/xen/ar
This patch adds the flag to enable Memory Protection Keys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
docs/misc/xen-command-line.markdown | 21 +
xen/arch/x86/setup.c| 7 +++
2 files changed, 28 insertions(+)
diff --git a/docs/mi
This patch adds functions to get pkeys value from PTE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/include/asm-x86/guest_pt.h| 7 +++
xen/include/asm-x86/page.h| 5 +
xen/include/asm-x86/x86_64/page.h | 19 +++
3 files changed, 31 inse
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
Re
This patch adds pkeys support for guest_walk_tables.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/mm/guest_walk.c | 65 +++
xen/include/asm-x86/hvm/hvm.h | 2 ++
2 files changed, 67 insertions(+)
diff --git a/xen/arch/
This patch adds pkeys support when setting CR4.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
xen/arch/x86/hvm/hvm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 0adafe9..0103bcb 100644
--- a/xen/ar
This patch adds pkeys support for cpuid handing.
Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is
CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
---
tools/libxc/xc_cpufeature.h | 2 ++
This patch adds functions to support PKRU access/write
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index f507f5e..427eb84 100644
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/proce
of Protection Keys can be found at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (10):
x86/hvm: pkeys, add pkeys support for cpuid handling
x86/hvm: pkeys, add pku support
This patch adds xstate support for pkeys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/include/asm-x86/xstate.h b/xen/include/asm-x86/xstate.h
index 4c690db..5674f3e 100644
--- a/xen/include/asm-x86/xstate.h
+++ b/xen/include/asm-x86/xstate.h
@@ -33,13 +33,14 @@
#
This patch adds functions to get pkeys value from PTE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/include/asm-x86/page.h b/xen/include/asm-x86/page.h
index 87b3341..1cdbfc8 100644
--- a/xen/include/asm-x86/page.h
+++ b/xen/include/asm-x86/page.h
@@ -93,6
This patch adds pkeys support for guest_walk_tables.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/arch/x86/mm/guest_walk.c b/xen/arch/x86/mm/guest_walk.c
index 773454d..7a7ae96 100644
--- a/xen/arch/x86/mm/guest_walk.c
+++ b/xen/arch/x86/mm/guest_walk.c
@@ -124,6 +
This patch disables pkeys for guest in non-paging mode, However XEN always uses
paging mode to emulate guest non-paging mode, To emulate this behavior, pkeys
needs to be manually disabled when guest switches to non-paging mode.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff
This patch adds pku support for x86_capability.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 35ef21b..04bf4fb 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -211,7 +211,7 @@ stati
This patch adds pkeys support for cpuid handing.
Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is
CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/tools/libxc/xc_cpufeature.h b/tools
This patch adds pkeys support when setting CR4
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 66917ff..953047f 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1911,6 +1911,7 @@ static unsigne
write and AD=1
--The access is a data write and WD=1 and either CR0.WP=1 or (CR0.WP=0 and
it is a user access)
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 9f5a6c6..73abb3b 100644
--- a/xen/arch/x86/traps.c
+++ b/xe
This patch adds the flag to enable Memory Protection Keys.
Signed-off-by: Huaitong Han <huaitong@intel.com>
diff --git a/docs/misc/xen-command-line.markdown
b/docs/misc/xen-command-line.markdown
index a565c1b..0ded4bf 100644
--- a/docs/misc/xen-command-line.markdown
+++ b/docs/mi
. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
---
ChangeLog:
V7:
delete uint64_t;
delete extern variable and keep variable static.
V6:
Add blank lines.
delete res_ticks[] and a wrong
. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
---
ChangeLog:
V6:
Add blank lines.
delete res_ticks[] and a wrong comment.
V5:
Ticks clock souce may be acpi_pm, so use common funciton
. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
---
ChangeLog:
V5:
Ticks clock souce may be acpi_pm, so use common funciton ticks_elapsed.
Taking every tick_to_ns outside spin_lock
. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
---
ChangeLog:
V4:
delete pointless initializers and hard tabs.
V3:
1.Don't use tick_to_ns inside lock in print_acpi_power.
2.Use 08
. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
---
ChangeLog:
V3:
1.Don't use tick_to_ns inside lock in print_acpi_power.
2.Use 08 padding in printk.
3.Merge two for circulation
. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index e639c99..e5fffe8 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
value. if margin of the second error cannot
make up for margin of the first error, the value of C0 would decrease.
Signed-off-by: Huaitong Han huaitong@intel.com
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index e639c99..fd80227 100644
--- a/xen/arch/x86/acpi
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