Hi Ian,
For ThunderX/arm64 this issue needs to be fixed.
Could you please comment on this?
I could think of below
1) Add new call for ARM under CONFIG_ARM_32/CONFIG_ARM_64
in vm_init() and manage map_pages_to_xen(va, 0, vm_low - nr, MAP_SMALL_PAGES);
with different function call for
On Wed, Feb 11, 2015 at 8:25 PM, Andrew Cooper
andrew.coop...@citrix.com wrote:
On 11/02/15 14:50, Vijay Kilari wrote:
Hi ,
I just glaced at the x86 code, here nr_irqs are set to 1024, which includes
normal irq's and MSI's. Memory for these descriptors are allocated at boot
time
Hi,
I want to know what is the criteria followed in Xen for scheduling VCPUs.
Assume below scenario:
- Run 2 VPCUs on 1 Physical CPU
- VCPUs does not trap on WFE or WFE ( either by WFI/WFE trap is
disabled in HCR OR no WFE/WFI in EL1 is executed).
In such scenario, does Xen assumes that
Hi,
Apart from OpenSUSE, I am looking for booting Dom0 with other distros like
Redhat Ubuntu. If so what is the procedure for installing xen tools on these
distros?
Regards
Vijay
___
Xen-devel mailing list
Xen-devel@lists.xen.org
From: Vijaya Kumar K vijaya.ku...@caviumnetworks.com
In pl011.c, when TX interrupt is received
serial_tx_interrupt() is called to push next
characters. If TX buffer is empty, serial_tx_interrupt()
does not disable TX interrupt and hence pl011 UART
irq handler pl011_interrupt() always sees TX
From: Vijaya Kumar K vijaya.ku...@caviumnetworks.com
On pl011.c when TX interrupt is received and
TX buffer is empty, TX interrupt is not disabled and
hence UART interrupt routine see TX interrupt always
in MIS register and cpu loops infinitly.
With this patch, mask and umask TX interrupt
when
Hi Tim,
On Thu, Dec 4, 2014 at 9:10 PM, Tim Deegan t...@xen.org wrote:
At 13:51 + on 04 Dec (1417697518), Julien Grall wrote:
On 04/12/14 03:50, Vijay Kilari wrote:
Hi Tim,
Hi Vijay,
I see that on uart interrupt, ICR is written to clear the all
interrupts except TX, RX and RX
Hi Tim,
I see that on uart interrupt, ICR is written to clear the all
interrupts except TX, RX and RX timeout. With this, cpu always finds
TX/RX is active and never
comes out of the loop.
With the below changes, TX, RX RTI are cleared before handling this
interrupts.
Is my observation is
501 - 508 of 508 matches
Mail list logo
