On Thu, 19 May 2016, Julien Grall wrote:
> Hi Peng,
>
> On 19/05/16 10:22, Peng Fan wrote:
> > CPU0 boots up secondary CPUs one by one. Before booting
> > one secondary CPU, CPU0 will assign hwid to smp_up_cpu
> > and flush cache. After the secondary CPU boots up,
>
> NIT: s/the/a/
>
> > CPU0
Hi Peng,
On 19/05/16 10:22, Peng Fan wrote:
CPU0 boots up secondary CPUs one by one. Before booting
one secondary CPU, CPU0 will assign hwid to smp_up_cpu
and flush cache. After the secondary CPU boots up,
NIT: s/the/a/
CPU0 will assign MPIDR_INVALID to smp_up_cpu and flush
cache.
There is
CPU0 boots up secondary CPUs one by one. Before booting
one secondary CPU, CPU0 will assign hwid to smp_up_cpu
and flush cache. After the secondary CPU boots up,
CPU0 will assign MPIDR_INVALID to smp_up_cpu and flush
cache.
There is no need for secondary CPUs to assign MPIDR_INVALID
to
