Re: [Xen-devel] [PATCH 1/4] arm: processor: rename iss to res0 in hsr_cond union

2017-07-28 Thread Julien Grall
Hi, On 07/28/2017 08:43 PM, Volodymyr Babchuk wrote: Name "iss" in this case was used not exactly correctly, because this is only part of HSR.ISS field. ARM refence manual denotes this s/refence/reference/ part of ISS as RES0 when it describes encoding for conditional exceptions. When you

[Xen-devel] [PATCH 1/4] arm: processor: rename iss to res0 in hsr_cond union

2017-07-28 Thread Volodymyr Babchuk
Name "iss" in this case was used not exactly correctly, because this is only part of HSR.ISS field. ARM refence manual denotes this part of ISS as RES0 when it describes encoding for conditional exceptions. Signed-off-by: Volodymyr Babchuk --- xen/include/asm-arm/processor.h | 2 +- 1 file chang