Hi Andrew,
On 16/10/17 15:38, Andrew Cooper wrote:
* x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
all state is actually set up. As it currently stands, d0v0 is eligible for
scheduling before its registers have been set. This is latent as we also
hold
On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we
>>> On 17.10.17 at 12:38, wrote:
> On 16/10/17 17:21, Jan Beulich wrote:
> On 16.10.17 at 18:07, wrote:
>>> On 16/10/17 16:41, Jan Beulich wrote:
>>> On 16.10.17 at 16:38, wrote:
> ---
On 16/10/17 17:21, Jan Beulich wrote:
On 16.10.17 at 18:07, wrote:
>> On 16/10/17 16:41, Jan Beulich wrote:
>>> >>> On 16.10.17 at 16:38, wrote:
--- a/xen/arch/x86/hvm/dom0_build.c
+++ b/xen/arch/x86/hvm/dom0_build.c
@@
On Mon, 16 Oct 2017, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we also
>hold a
On 16/10/17 16:51, Roger Pau Monné wrote:
> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
>> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>>all state is actually set up. As it currently stands, d0v0 is eligible
>> for
>>scheduling before
>>> On 16.10.17 at 18:07, wrote:
> On 16/10/17 16:41, Jan Beulich wrote:
>> >>> On 16.10.17 at 16:38, wrote:
>>> --- a/xen/arch/x86/hvm/dom0_build.c
>>> +++ b/xen/arch/x86/hvm/dom0_build.c
>>> @@ -614,6 +614,7 @@ static int __init
On 16/10/17 16:39, Jan Beulich wrote:
On 16.10.17 at 16:49, wrote:
>> On 16/10/17 15:44, Wei Liu wrote:
>>> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
* x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
all
On 16/10/17 16:41, Jan Beulich wrote:
> >>> On 16.10.17 at 16:38, wrote:
>> --- a/xen/arch/x86/hvm/dom0_build.c
>> +++ b/xen/arch/x86/hvm/dom0_build.c
>> @@ -614,6 +614,7 @@ static int __init pvh_setup_cpus(struct domain *d,
>> paddr_t entry,
>>
>>
On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we
>>> On 16.10.17 at 16:38, wrote:
> --- a/xen/arch/x86/hvm/dom0_build.c
> +++ b/xen/arch/x86/hvm/dom0_build.c
> @@ -614,6 +614,7 @@ static int __init pvh_setup_cpus(struct domain *d,
> paddr_t entry,
>
> update_domain_wallclock_time(d);
>
> +
>>> On 16.10.17 at 16:49, wrote:
> On 16/10/17 15:44, Wei Liu wrote:
>> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
>>> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>>>all state is actually set up. As it currently
On Mon, Oct 16, 2017 at 03:49:54PM +0100, Andrew Cooper wrote:
> On 16/10/17 15:44, Wei Liu wrote:
> > On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> >> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
> >>all state is actually set up. As it
On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>all state is actually set up. As it currently stands, d0v0 is eligible for
>scheduling before its registers have been set. This is latent as we
* x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
all state is actually set up. As it currently stands, d0v0 is eligible for
scheduling before its registers have been set. This is latent as we also
hold a systemcontroller pause reference at the time which
On 16/10/17 15:44, Wei Liu wrote:
> On Mon, Oct 16, 2017 at 03:38:03PM +0100, Andrew Cooper wrote:
>> * x86 PV and ARM dom0's must not clear _VPF_down from v->pause_flags until
>>all state is actually set up. As it currently stands, d0v0 is eligible
>> for
>>scheduling before its
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