On Thu, 2017-03-16 at 11:23 -0700, Krish Sadhukhan wrote:
> The Intel SDM also mentions POP-SS. Are you planning to do it via
> another patch ?
(SDM from Dec 2016) In "Table 24-3. Format of Interruptibility State"
it reads "This document uses the term “blocking by MOV SS,” but it
applies equally
The Intel SDM also mentions POP-SS. Are you planning to do it via
another patch ?
Also, I was wondering if it makes more sense to rename the new enum code as
VMX_INSN_VMENTRY_BLOCKED
since it can then also be used for POP-SS.
-Krish
On 03/13/2017 03:51 AM, Sergey Dyasli wrote:
Intel
> From: Sergey Dyasli [mailto:sergey.dya...@citrix.com]
> Sent: Monday, March 13, 2017 6:52 PM
>
> Intel SDM states that if there is a current VMCS and there is MOV-SS blocking,
> VMFailValid occurs and control passes to the next instruction.
>
> Implement such behaviour for nested vmlaunch and
On 13/03/17 10:51, Sergey Dyasli wrote:
> Intel SDM states that if there is a current VMCS and there is MOV-SS
> blocking, VMFailValid occurs and control passes to the next instruction.
>
> Implement such behaviour for nested vmlaunch and vmresume.
>
> Signed-off-by: Sergey Dyasli
Intel SDM states that if there is a current VMCS and there is MOV-SS
blocking, VMFailValid occurs and control passes to the next instruction.
Implement such behaviour for nested vmlaunch and vmresume.
Signed-off-by: Sergey Dyasli
---
xen/arch/x86/hvm/vmx/vvmx.c