Hi Ian,
On 25/11/15 12:29, Ian Campbell wrote:
> On Tue, 2015-11-24 at 17:14 +, Ian Campbell wrote:
>> @@ -507,10 +507,12 @@ static int vgic_v2_distr_mmio_write(struct vcpu
>>> *v,
>>> mmio_info_t *info,
>>>
>>> case GICD_ICFGR: /* SGIs */
>>> goto write_ignore_32;
>>> -
On Tue, 2015-11-24 at 17:14 +, Ian Campbell wrote:
> @@ -507,10 +507,12 @@ static int vgic_v2_distr_mmio_write(struct vcpu
> > *v,
> > mmio_info_t *info,
> >
> > case GICD_ICFGR: /* SGIs */
> > goto write_ignore_32;
> > -case GICD_ICFGR + 1: /* PPIs */
> > +
> > +case
On Wed, 2015-11-18 at 17:27 +, Julien Grall wrote:
> Each ITARGETSR register are 4-byte wide and the offset is in byte.
"is 4-bytes" ... "is in bytes".
>
> The current implementation is computing the offset of ICFGR1 and ICFG2
> wonrgly result to emulate only the first 2 byte of the ICFGR
Each ITARGETSR register are 4-byte wide and the offset is in byte.
The current implementation is computing the offset of ICFGR1 and ICFG2
wonrgly result to emulate only the first 2 byte of the ICFGR range
read-only. The rest will be treated as read-write.
For convenience introduce ITARGETSR1 and
