Re: [Xen-devel] [PATCH v3] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

Hi Jan, On 05/05/17 11:16, Jan Beulich wrote: On 04.05.17 at 23:30, wrote: Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General Protection Fault and thus results in a hypervisor crash. This behavior has been observed on two generations of Intel

Re: [Xen-devel] [PATCH v3] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

> From: Jan Beulich > Sent: Friday, May 5, 2017 6:16 PM > > >>> On 04.05.17 at 23:30, wrote: > > Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General > > Protection Fault and thus results in a hypervisor crash. This behavior has > > been observed on

Re: [Xen-devel] [PATCH v3] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

>>> On 04.05.17 at 23:30, wrote: > Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General > Protection Fault and thus results in a hypervisor crash. This behavior has > been observed on two generations of Intel processors namely, Haswell and >

[Xen-devel] [PATCH v3] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General Protection Fault and thus results in a hypervisor crash. This behavior has been observed on two generations of Intel processors namely, Haswell and Broadwell. Other Intel processor generations were not tested. However, it