On 29.05.15 at 04:40, chao.p.p...@linux.intel.com wrote:
On Thu, May 28, 2015 at 01:54:39PM +0100, Jan Beulich wrote:
On 21.05.15 at 10:41, chao.p.p...@linux.intel.com wrote:
+
+if ( !cpu_has(c, X86_FEATURE_CAT) )
+return;
+
+socket = cpu_to_socket(cpu);
+if (
On Thu, May 28, 2015 at 01:54:39PM +0100, Jan Beulich wrote:
On 21.05.15 at 10:41, chao.p.p...@linux.intel.com wrote:
+
+if ( !cpu_has(c, X86_FEATURE_CAT) )
+return;
+
+socket = cpu_to_socket(cpu);
+if ( test_bit(socket, cat_socket_enable) )
+return;
+
On 21.05.15 at 10:41, chao.p.p...@linux.intel.com wrote:
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -19,14 +19,25 @@
#include asm/psr.h
#define PSR_CMT(10)
+#define PSR_CAT(11)
+
+struct psr_cat_socket_info {
+unsigned int cbm_len;
+unsigned int
Detect Intel Cache Allocation Technology(CAT) feature and store the
cpuid information for later use. Currently only L3 cache allocation is
supported. The L3 CAT features may vary among sockets so per-socket
feature information is stored. The initialization can happen either at
boot time or when
