On Mon, 2016-05-16 at 16:23 +0800, He Chen wrote:
> As Andrew said, CLOS is currently managed per-domain in Xen and it
> works
> well so far. So in initial design, I am inclined to continue this
> behavior (per-socket) to L2 CAT to keep the consistency between L2
> and
> L3 CAT. Any thoughts?
>
On Fri, May 13, 2016 at 06:17:53PM +0200, Dario Faggioli wrote:
> On Fri, 2016-05-13 at 10:23 +0100, Andrew Cooper wrote:
> > On 13/05/16 09:55, Jan Beulich wrote:
> > >
> > > But anyway, L2 or L3 - I can't see how this context switching would
> > > DTRT when there are vCPU-s of different domains
On Fri, 2016-05-13 at 10:23 +0100, Andrew Cooper wrote:
> On 13/05/16 09:55, Jan Beulich wrote:
> >
> > But anyway, L2 or L3 - I can't see how this context switching would
> > DTRT when there are vCPU-s of different domains on the same
> > socket (or core, if L2s and MSRs were per-core): The one
On 13/05/16 09:55, Jan Beulich wrote:
On 13.05.16 at 09:43, wrote:
>> On 13/05/2016 07:48, Jan Beulich wrote:
>> On 13.05.16 at 08:26, wrote:
On Thu, May 12, 2016 at 04:05:36AM -0600, Jan Beulich wrote:
On 12.05.16 at
>>> On 13.05.16 at 09:43, wrote:
> On 13/05/2016 07:48, Jan Beulich wrote:
> On 13.05.16 at 08:26, wrote:
>>> On Thu, May 12, 2016 at 04:05:36AM -0600, Jan Beulich wrote:
>>> On 12.05.16 at 11:40, wrote:
>
On 13/05/2016 07:48, Jan Beulich wrote:
On 13.05.16 at 08:26, wrote:
>> On Thu, May 12, 2016 at 04:05:36AM -0600, Jan Beulich wrote:
>> On 12.05.16 at 11:40, wrote:
We plan to bring new PQoS feature called Intel L2 Cache Allocation
>>> On 13.05.16 at 08:26, wrote:
> On Thu, May 12, 2016 at 04:05:36AM -0600, Jan Beulich wrote:
>> >>> On 12.05.16 at 11:40, wrote:
>> > We plan to bring new PQoS feature called Intel L2 Cache Allocation
>> > Technology (L2 CAT) to Xen.
>> >
>>
On Thu, May 12, 2016 at 04:05:36AM -0600, Jan Beulich wrote:
> >>> On 12.05.16 at 11:40, wrote:
> > % Intel L2 Cache Allocation Technology (L2 CAT) Feature
> > % Revision 1.0
> >
> > \clearpage
> >
> > Hi all,
> >
> > We plan to bring new PQoS feature called Intel L2
On 12/05/16 10:40, He Chen wrote:
> % Intel L2 Cache Allocation Technology (L2 CAT) Feature
> % Revision 1.0
>
> \clearpage
>
> Hi all,
>
> We plan to bring new PQoS feature called Intel L2 Cache Allocation
> Technology (L2 CAT) to Xen.
>
> L2 CAT is supported on Atom codename Goldmont and beyond.
>>> On 12.05.16 at 11:40, wrote:
> % Intel L2 Cache Allocation Technology (L2 CAT) Feature
> % Revision 1.0
>
> \clearpage
>
> Hi all,
>
> We plan to bring new PQoS feature called Intel L2 Cache Allocation
> Technology (L2 CAT) to Xen.
>
> L2 CAT is supported on Atom
% Intel L2 Cache Allocation Technology (L2 CAT) Feature
% Revision 1.0
\clearpage
Hi all,
We plan to bring new PQoS feature called Intel L2 Cache Allocation
Technology (L2 CAT) to Xen.
L2 CAT is supported on Atom codename Goldmont and beyond. “Big-core”
Xeon does not support L2 CAT in current
% Intel L2 Cache Allocation Technology (L2 CAT) Feature
% Revision 1.0
\clearpage
Hi all,
We plan to bring new PQoS feature called Intel L2 Cache Allocation
Technology (L2 CAT) to Xen.
L2 CAT is supported on Atom codename Goldmont and beyond. “Big-core”
Xeon does not support L2 CAT in current
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