On Tue, Jun 27, 2017 at 05:44:23AM -0600, Jan Beulich wrote:
> >>> Roger Pau Monne 06/27/17 12:23 PM >>>
> >On Fri, May 26, 2017 at 09:26:03AM -0600, Jan Beulich wrote:
> >> > +static int vpci_msi_address_upper_write(struct pci_dev *pdev, unsigned
> >> > int reg,
> >> > +
>>> Roger Pau Monne 06/27/17 12:23 PM >>>
>On Fri, May 26, 2017 at 09:26:03AM -0600, Jan Beulich wrote:
>> >>> On 27.04.17 at 16:35, wrote:
>> > +pinfo = pirq_info(current->domain, arch->pirq + entry);
>> > +ASSERT(pinfo);
>> > +
>> > +irq = pinfo->arch.irq;
>> > +ASSERT(irq < nr_
On Fri, May 26, 2017 at 09:26:03AM -0600, Jan Beulich wrote:
> >>> On 27.04.17 at 16:35, wrote:
> > Add handlers for the MSI control, address, data and mask fields in order to
> > detect accesses to them and setup the interrupts as requested by the guest.
> >
> > Note that the pending register is
>>> On 27.04.17 at 16:35, wrote:
> Add handlers for the MSI control, address, data and mask fields in order to
> detect accesses to them and setup the interrupts as requested by the guest.
>
> Note that the pending register is not trapped, and the guest can freely
> read/write to it.
>
> Whether
