will get objects added by Makefile and add their
dependencies to check list.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
v1 -> v2:
- Use a generic method instead of changing Makefiles
---
xen/Rules.mk | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/xen/R
On 7 June 2016 at 21:18, Konrad Rzeszutek Wilk <konrad.w...@oracle.com> wrote:
> On Tue, Jun 07, 2016 at 12:34:43PM +0800, Wei Chen wrote:
>> In current Xen build rules, the build system will only check the
>> dependencies in current folder and obj-y generated dependenci
Hi,
On 8 June 2016 at 00:24, Wei Liu <wei.l...@citrix.com> wrote:
> On Tue, Jun 07, 2016 at 05:01:35PM +0100, Ian Jackson wrote:
>> Wei Chen writes ("[RFC v2] xen/arm: build: add missed dependency for
>> head.S"):
>> > In current Xen build
ild system will not recompile the head.S.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
In my mind, the better way to fix this bug is converting the DEPS from
ALL_OBJS. But I am afraid of the impact. I am not sure whether there
are some dependencies are not generated from obj files.
Hi Shanker,
On 27 May 2016 at 22:56, Julien Grall wrote:
> Hello Shanker,
>
> On 27/05/16 15:01, Shanker Donthineni wrote:
>>
>> On 05/27/2016 08:04 AM, Julien Grall wrote:
>>>
>>> On 27/05/16 01:28, Shanker Donthineni wrote:
The ARM Server Base System
of ARM ARM
(DDI 0487A.i).
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
v2-->v3:
1. Add version information of mentioned ARM ARM.
v1-->v2: Address Julien's comments
1. Fix typos in commit messages.
2. Explain valid MPIDR_HWID_MASK value in AArch64.
3. Simply explain mov immedi
In AArch32, MPIDR bit 31 is defined as multiprocessing extensions bit.
But in AArch64, this bit is always RES1. So the value check for this
bit is no longer necessary in AArch64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
v2--v3:
1. Fix a typo in commit messages.
2. Add Julien's Re
In ARM64 the MPIDR register is mapped to MPIDR_EL1, and the register
bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
as 32-bit register.
We have to provide correct accessing to this register to avoid
unexpected issues that is caused by incorrect MPIDR value.
Wei Chen (4
expands to 64-bits and then the cpu_logical_map will overflow.
Change the variable type of cpu_logical_map to register_t will make
cpu_logical_map to store hardware IDs correctly on ARM32 and ARM64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
v2-->v3:
1. Update verion number.
v1--&g
-by: Wei Chen <wei.c...@linaro.org>
---
v2-->v3:
Update version numnber.
v1-->v2:
Add Julien's reviewed-by.
---
xen/include/asm-arm/processor.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 7de9
Hi Stefano,
On 30 May 2016 at 21:24, Stefano Stabellini <sstabell...@kernel.org> wrote:
> On Mon, 30 May 2016, Wei Chen wrote:
>> In ARM64 the MPIDR register is mapped to MPIDR_EL1, and the register
>> bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
-by: Wei Chen <wei.c...@linaro.org>
Reviewed-by: Julien Grall <julien.gr...@arm.com>
---
v3-->v4:
Add missed Reviewed-by tag.
v2-->v3:
Update version numnber.
v1-->v2:
Add Julien's reviewed-by.
---
xen/include/asm-arm/processor.h | 3 ++-
1 file changed, 2 insertions(+), 1 de
In ARM64 the MPIDR register is mapped to MPIDR_EL1, and the register
bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
as 32-bit register.
We have to provide correct accessing to this register to avoid
unexpected issues that is caused by incorrect MPIDR value.
Wei Chen (4
of ARM ARM
(DDI 0487A.i).
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
v3-->v4:
1. Update version number.
v2-->v3:
1. Add version information of mentioned ARM ARM.
v1-->v2: Address Julien's comments
1. Fix typos in commit messages.
2. Explain valid MPIDR_HWID_MASK value in AAr
In AArch32, MPIDR bit 31 is defined as multiprocessing extensions bit.
But in AArch64, this bit is always RES1. So the value check for this
bit is no longer necessary in AArch64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
Reviewed-by: Julien Grall <julien.gr...@arm.com>
---
v3-
expands to 64-bits and then the cpu_logical_map will overflow.
Change the variable type of cpu_logical_map to register_t will make
cpu_logical_map to store hardware IDs correctly on ARM32 and ARM64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
Acked-by: Julien Grall <julien.gr...@arm.co
-by: Wei Chen <wei.c...@linaro.org>
Reviewed-by: Julien Grall <julien.gr...@arm.com>
---
v2: Add Julien's reviewed-by.
---
xen/include/asm-arm/processor.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/proce
In ARM64 the MPIDR register is mapped to MPIDR_EL1, and the register
bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
as 32-bit register.
We have to provide correct accessing to this register to avoid
unexpected issues that is caused by incorrect MPIDR value.
Wei Chen (4
. But neither
of this value and its bitwise invert value can be used in mov instruction
with the encoding of {imm16:shift} or {imms:immr}. So we have to use ldr
to load the bitwise invert value to register.
The details of mov immediate encoding are listed in ARMv8 ARM C4.2.5.
Signed-off-by: Wei Chen
In AArch32, MPIDR bit31 is defined as multiprocessing extensions bit.
But in AArch64, this bit is always RES1. So the value check for this
bit is no longer necessary in AArch64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
v2: Make clear the status of MPIDR.SMP bit in AArch32 and A
Hi Shanker,
On 31 May 2016 at 22:02, Shanker Donthineni wrote:
> The ARM Server Base System Architecture describes a generic UART
> interface. It doesn't support clock control registers, modem
> control, DMA and hardware flow control features. So, extend the
> driver
On 27 May 2016 at 18:50, Julien Grall <julien.gr...@arm.com> wrote:
> Hi Wei,
>
> On 26/05/16 08:58, Wei Chen wrote:
>>
>> Currently, MPIDR_HWID_MASK is using the bit definition of AArch32 MPIDR.
>> From ARMv8 ARM we can see there are 4 levels of affinity on AAr
d,
> const struct dt_device_node *v2m = NULL;
> const struct v2m_data *v2m_data;
>
> +/* It is not necessary to create the node if there are not GICv2m frames
> */
> +if ( list_empty(_info) )
> +return 0;
> +
> /* The sub-nodes require th
Hi Julien,
On 27 April 2016 at 17:40, Julien Grall <julien.gr...@arm.com> wrote:
>
>
> On 27/04/2016 07:05, Wei Chen wrote:
>>
>> Hi Julien,
>
>
> Hi Wei,
>
>> On 26 April 2016 at 18:49, Julien Grall <julien.gr...@arm.com>
Hi Julien,
On 26 April 2016 at 18:49, Julien Grall <julien.gr...@arm.com> wrote:
> Hello Wei,
>
> On 25/04/2016 10:39, Wei Chen wrote:
>>
>> This patch adds v2m extension support in GIC-v2 driver. The GICv2 driver
>> detects the MSI frames from device tree and cre
support, the dom0 kernel can do GICv2m frame
setup and initialization.
This patch is based on the GICv2m patch of Suravee Suthikulpanit:
[PATCH 2/2] xen/arm: gicv2: Adding support for GICv2m in Dom0
http://lists.xen.org/archives/html/xen-devel/2015-04/msg02613.html
Signed-off-by: Wei Chen <we
Hi Julien,
On 23 April 2016 at 02:29, Julien Grall <julien.gr...@arm.com> wrote:
> Hi Wei,
>
>
> On 21/04/16 09:24, Wei Chen wrote:
>
>> This patch adds v2m extension support in GIC-v2 driver. The GICv2 driver
>> detects the MSI frames from device tree and cre
extension support, the domain0 kernel can do GICv2m
frame setup and initialization.
This patch is based on the GICv2m patch of Suravee Suthikulpanit:
[PATCH 2/2] xen/arm: gicv2: Adding support for GICv2m in Dom0
http://lists.xen.org/archives/html/xen-devel/2015-04/msg02613.html
Signed-off-by: Wei
Sorry, I forget to change to the plain text mode.
On 25 April 2016 at 17:45, Stefano Stabellini <sstabell...@kernel.org> wrote:
> Hello Wei,
>
> could you please send email replies in plain text (rather than html)?
>
> Thanks,
>
> Stefano
>
> On Mon, 25 Apr 2
Hi Julien
On 23 April 2016 at 02:29, Julien Grall <julien.gr...@arm.com> wrote:
> Hi Wei,
>
>
> On 21/04/16 09:24, Wei Chen wrote:
>>
>> This patch adds v2m extension support in GIC-v2 driver. The GICv2 driver
>> detects the MSI frames from device tree and
In ARM64, the MPIDR multiprocessing extensions bit is reserved to 1.
So, the value check for this bit is no longer necessary on ARM64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
xen/arch/arm/arm64/head.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/xen/arch/arm/arm64/head.S
this value to register.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
xen/arch/arm/arm64/head.S | 2 +-
xen/include/asm-arm/processor.h | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index d5831f2..3
expands to 64-bits and then the cpu_logical_map will overflow.
Change the the variable type of cpu_logical_map to register_t will make
cpu_logical_map to store hardware ID correctly on ARM32 and ARM64.
Signed-off-by: Wei Chen <wei.c...@linaro.org>
---
xen/arch/arm/gic-v3.c | 2 +
In ARM64 the MPIDR register is mapped to MPIDR_EL1, and the register
bits are expanded to 64-bits. But Xen 64-bit ARM code treats this it
as 32-bit register.
We have to provide correct accessing to this register to avoid
unexpected issues that is caused by incorrect MPIDR value.
Wei Chen (4
-by: Wei Chen <wei.c...@linaro.org>
---
xen/include/asm-arm/processor.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 7de9c8e..b4cce7e 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/a
code...
(XEN) *** LOADING DOMAIN 0 ***
Tested-by: Wei Chen <wei.c...@linaro.org>
Regards.
On 6 May 2016 at 00:34, Julien Grall <julien.gr...@arm.com> wrote:
> Hello,
>
> Some of the processor erratum will require to modify code sequence. As those
> modifications ma
Hi Julien,
On 17 May 2016 at 00:30, Julien Grall wrote:
> Hi Wei,
>
>
> On 16/05/16 16:47, Wei Liu wrote:
>>
>> On Mon, May 16, 2016 at 05:03:54PM +0200, Edgar E. Iglesias wrote:
>>>
>>> From: "Edgar E. Iglesias"
>>>
>>> I'm sending this as a v2
Hi Julien,
This code looks good to me, and I have tested that
the deadlock is fixed by this patch.
Reviewed-and-Tested-by: Wei Chen <wei.c...@arm.com>
Original:
(XEN) smmu: /smb/smmu@e080: P2M IPA size not supported (P2M=44 SMMU=40)!
(XEN) I/O virtualisation disabled
(XEN) Reque
Hi Julien,
This code looks good to me.
Reviewed-by: Wei Chen <wei.c...@arm.com>
On 2016/5/16 22:08, Julien Grall wrote:
Since commit 4b25423a "arch/arm: unmap partially-mapped memory regions",
Xen has been undoing the P2M mappings when an error occurred during
insertion or m
. Is it a security risk?
On 2016/5/17 13:45, Wei Chen wrote:
Hi Julien,
This code looks good to me, and I have tested that
the deadlock is fixed by this patch.
Reviewed-and-Tested-by: Wei Chen <wei.c...@arm.com>
Original:
(XEN) smmu: /smb/smmu@e080: P2M IPA size not supported (P2M=44
SMMU=40)!
(XE
extension support, the domain0 kernel can do GICv2m
frame setup and initialization.
This patch is based on the GICv2m patch of Suravee Suthikulpanit:
[PATCH 2/2] xen/arm: gicv2: Adding support for GICv2m in Dom0
http://lists.xen.org/archives/html/xen-devel/2015-04/msg02613.html
Signed-off-by: Wei
switch (action) {
>>> case CPU_UP_PREPARE:
>>> +if (cpu_acpi_id(cpu) != U32_MAX)
>>> +per_cpu(xen_vcpu_id, cpu) = cpu_acpi_id(cpu);
>>> +else
>>> +per_cpu(xen_vcpu_id, cpu) = cpu;
>>
>> I have not tried myself. But looking at the code, the notifie
end Kernel panic - not syncing: Attempted to kill
init! exitcode=0x000b
--
Regards,
Wei Chen
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do no
source trees.
1. https://lists.xenproject.org/archives/html/xen-devel/2017-03/msg01939.html
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
xen/arch/arm/alternative.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/alternative.c b/xen/
source trees.
1. https://lists.xenproject.org/archives/html/xen-devel/2017-03/msg01939.html
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v1-v2:
1. Show an example to explain how to hit the BUG(); in
branch_insn_requires_update
2. Remove the 'new instructions' in commit mes
nation. Now I know :)
> Cheers,
>
> On 23/03/17 09:43, Wei Chen wrote:
>> While I was using the alternative patching in the SErrors patch series [1].
>> I used a branch instruction as alternative instruction.
>>
>> ALTE
Hi Julien,
On 2017/3/24 3:19, Julien Grall wrote:
> Hi Wei,
>
> NIT: title: please add a space between : and alternative.
>
Ok.
> On 23/03/17 09:43, Wei Chen wrote:
>> While I was using the alternative patching in the SErrors patch series [1].
>> I used a branch
Hi Stefano,
On 2017/3/24 8:10, Stefano Stabellini wrote:
> On Thu, 23 Mar 2017, Julien Grall wrote:
>> Hi Wei,
>>
>> On 23/03/17 03:13, Wei Chen wrote:
>>> On 2017/3/23 6:22, Stefano Stabellini wrote:
>>>> On Wed, 22 Mar 2017, Julien Grall wrote:
>&g
he page.h of ARM32 doesn't include alternative.h,
and we don't have the reason to include it to ARM32 page.h now. So we
have to include the alternative.h directly in livepatch.c.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.w...@oracle.com>
---
v1->
ists.xenproject.org/archives/html/xen-devel/2017-03/msg01939.html
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
Notes:
This bug will affect the staging, staging-4.8 and stable-4.8 source trees.
---
v2->v3
1. Fix typos.
2. Explain this bug only happening when booting Xen in commit message
Hi Julien,
On 2017/3/24 18:48, Julien Grall wrote:
> On 03/17/2017 06:35 AM, Wei Chen wrote:
>> Hi Julien,
>
> Hi Wei,
>
> Sorry for the late answer, I missed that e-mail.
>
>> On 2017/3/17 6:24, Julien Grall wrote:
>>> On 03/16/2017 09:53 AM, Wei Chen wrot
to restore ELR and CPSR from stack at the same time. We have to use
ldr to restore them separately.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v1->v2:
1. Use more accurate words in the commit message.
2. Remove pointless comment message in cpu_user_regs.
3. Explain the changes of the regis
.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
xen/arch/arm/arm64/domctl.c | 6 ++
xen/arch/arm/domain.c| 5 +
xen/arch/arm/domain_build.c | 7 +++
xen/arch/arm/p2m.c | 5 -
xen/include/asm-arm/domain.h | 1 +
5 files changed, 19 insertions(+), 5 del
to restore the HCR_EL2 for each vCPU. Of course, the value of each
vCPU's HCR_EL2 should be adjusted to have proper HCR_EL2.RW bit in this
function. In the later patch of this series, we will set the HCR_EL2.RW
for each vCPU while the domain is creating.
Signed-off-by: wei chen <wei.c...@arm.com>
in dom0's context. So checking vwfi in init_trap is pointless.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
I have tried to remove HCR_EL2 setting from init_traps, but the Xen will
hang at the place of creating domain0. The console hot key can work, so
the Xen is alive, not panic.
---
xe
overhead of the dsb/isb pairs.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
v1->v2:
1. Correct words and syntax in the commit message and docs.
2. Add Stefano's Reviewed-by tag.
---
docs/misc/xen-co
. This would be useful when
VM introspection will gain support of SVC32/64 trapping.
This helper will be used by the later patches in this series, we
use #if 0 to disable it in this patch temporarily to remove the
warning message of unused function from compiler.
Signed-off-by: Wei Chen <wei.c...@arm.
to avoid receiving nested asynchronous abort, we don't
unmask Abort/SError bit in hyp_error and trap_data_abort.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
xen/arch/arm/arm32/entry.S | 15 ++-
xen/arch/arm/arm64/
ntroduce this helper to synchronize SErrors while
returning to guest and doing context switch.
This function should be used out of trap.c in later patch of this
series. We have to export this helper in header file.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell
e files.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v1->v2:
1. Added a new flag in cpu_hwcaps to avoid using serror_op to skip
synchronizing SError in context switch.
2. Update commit message to explain why we added this cpu_hwcaps.
---
xen/arch/arm/domain.c| 14 +++
in separated patchs.
Wei Chen (19):
xen/arm: Save ESR_EL2 to avoid using mismatched value in syndrome
check
xen/arm: Remove vwfi while setting HCR_EL2 in init_traps
xen/arm: Move parse_vwfi from trap.c to domain.c
xen/arm: Restore HCR_EL2 register
xen/arm: Avoid setting/clearing HCR
cpu_hwcaps.
So, we introduce this initcall to guarantee the cpu_hwcaps can be
updated no matter the serror parameter is placed in the command line
or not.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v1->v2:
1. Explain this initcall is to future-proof the code in commit
m
n to guest.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
xen/arch/arm/traps.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 9b4546e..f3d794e 100644
--- a/xen/arch
.
The ARM32 supports the alternative patching feature. We can use an
ALTERNATIVE to avoid checking option at every trap. We added a new
cpufeature named "SKIP_CHECK_PENDING_VSERROR". This feature will be
enabled when the option is not diverse.
Signed-off-by: Wei Chen <wei.c...@arm.com>
-
abort_guest_exit_start and
abort_guest_exit_end. After we moved this macro to common header, we
should export these two symbols to other source files that will use
VABORT_GEN_BY_GUEST macro. So we change these two symbols to global.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v1->v2:
1. Explain
ad removed the HCR_EL2 setting
from init_traps. Keep parse_vwfi in trap.c is pointless. And we will set
the HCR_EL2 for each domain individually while it's creating in the later
patch of this series. So we move parse_vwfi to domain.c for preparation.
Signed-off-by: Wei Chen <wei.c...@arm.com>
-
The guest generated external data/instruction aborts can be treated
as guest SErrors. We already have a handler to handle the SErrors,
so we can reuse this handler to handle guest external aborts.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@k
, that would be a bug.
In the new helpers, we have used the function "inject_vabt_exception"
which was disabled by "#if 0" before. Now, we can remove the "#if 0"
to make this function to be available.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefan
he page.h of ARM32 doesn't include alternative.h,
and we don't have the reason to include it to ARM32 page.h now. So we
have to include the alternative.h directly in livepatch.c.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.w...@oracle.com>
---
to restore
it to HCR_EL2 when context switch to this guest. This is achieved
by writing saved HCR_EL2 value in guest context back to HCR_EL2
register before return to guest. This had been done by the patch
of "Restore HCR_EL2 register".
Signed-off-by: Wei Chen <wei.c...@arm.com>
Revi
.
The ARM64 supports the alternative patching feature. We can use an
ALTERNATIVE to avoid checking option at every trap. We added a new
cpufeature named "SKIP_CHECK_PENDING_VSERROR". This feature will be
enabled when the option is not diverse.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Revi
We have introduced two helpers to handle the guest/hyp SErrors:
do_trap_guest_serror and do_trap_guest_hyp_serror. These handlers
can take the role of do_trap_guest_serror and reduce the assembly
code in the same time. So we use these two helpers to replace it
and drop it now.
Signed-off-by: Wei
Hi Stefano,
On 2017/3/23 6:22, Stefano Stabellini wrote:
> On Wed, 22 Mar 2017, Julien Grall wrote:
>> Hi Wei,
>>
>> On 22/03/17 08:49, Wei Chen wrote:
>>> Hi Stefano,
>>>
>>> On 2017/3/21 5:38, Stefano Stabellini wrote:
>>>> On
Hi Julien,
On 2017/3/29 22:07, Julien Grall wrote:
>
>
> On 29/03/17 10:28, Wei Chen wrote:
>> Hi Julien,
>>
>> On 2017/3/29 16:40, Julien Grall wrote:
>>> Hi Wei,
>>>
>>> On 28/03/2017 08:23, Wei Chen wrote:
>>>> diff --git a/
Hi Julien,
On 2017/3/29 16:40, Julien Grall wrote:
> Hi Wei,
>
> On 28/03/2017 08:23, Wei Chen wrote:
>> diff --git a/xen/include/asm-arm/arm32/insn.h
>> b/xen/include/asm-arm/arm32/insn.h
>> new file mode 100644
>> index 000..4cda69e
>> --- /dev/
On 2017/3/31 16:39, Julien Grall wrote:
> Hi Wei,
>
> On 03/31/2017 03:10 AM, Wei Chen wrote:
>> Hi Julien and Stefano,
>>
>> On 2017/3/31 6:03, Stefano Stabellini wrote:
>>> On Thu, 30 Mar 2017, Julien Grall wrote:
>>>> Hi Wei,
>>>>
&g
Hi Julien,
On 2017/3/31 1:39, Julien Grall wrote:
> Hi Wei,
>
> On 30/03/17 10:13, Wei Chen wrote:
>> In order to distinguish guest-generated SErrors from hypervisor-generated
>> SErrors we have to place SError checking code in every EL1 -> EL2 paths.
>> That will
On 2017/3/31 6:29, Stefano Stabellini wrote:
> On Thu, 30 Mar 2017, Julien Grall wrote:
>> Hi Wei,
>>
>> On 30/03/17 10:13, Wei Chen wrote:
>>> We will set HCR_EL2 for each domain individually at the place where each
>>> domain is created. vwfi will aff
On 2017/3/31 19:06, Julien Grall wrote:
>
>
> On 31/03/17 11:55, Wei Chen wrote:
>> Hi Julien,
>
> Hi Wei,
>
>> On 2017/3/31 2:38, Julien Grall wrote:
>>>
>>>
>>> On 30/03/17 19:32, Julien Grall wrote:
>>>> On 30/03/17 19:28,
Hi Julien,
On 2017/3/31 2:38, Julien Grall wrote:
>
>
> On 30/03/17 19:32, Julien Grall wrote:
>> On 30/03/17 19:28, Julien Grall wrote:
>>> Hi Wei,
>>>
>>> On 30/03/17 10:13, Wei Chen wrote:
>>>> +void synchronize_serror(void)
>>>
&
in separated patchs.
Wei Chen (19):
xen/arm: Save ESR_EL2 to avoid using mismatched value in syndrome
check
xen/arm: Introduce a helper to get default HCR_EL2 flags
xen/arm: Set and restore HCR_EL2 register for each vCPU separately
xen/arm: Avoid setting/clearing HCR_RW at every context
to restore
it to HCR_EL2 when context switch to this guest. This is achieved
by writing saved HCR_EL2 value in guest context back to HCR_EL2
register before return to guest. This had been done by the patch
of "Restore HCR_EL2 register".
Signed-off-by: Wei Chen <wei.c...@arm.com>
Revi
.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Acked-by: Julien Grall <julien.gr...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
xen/arch/arm/arm64/domctl.c | 6 ++
xen/arch/arm/domain.c| 5 +
xen/arch/arm/domain_build.c | 7 +++
to restore ELR and CPSR from stack at the same time. We have to use
ldr to restore them separately.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
Note:
This patch is a bug fix, this bug affects the 4.8 and 4.7 source trees
too.
v2->v3:
1. Add note to the commit message.
2. Read ESR_EL2 value
We want to add HCR_EL2 register to Xen context switch. And each copy
of HCR_EL2 in vcpu structure will be initialized with the same set
of trap flags as the HCR_EL2 register. We introduce a helper here to
represent these flags to be reused easily.
Signed-off-by: Wei Chen <wei.c...@arm.
to restore the HCR_EL2 for each vCPU. Of course, the value of each
vCPU's HCR_EL2 should be adjusted to have proper HCR_EL2.RW bit in this
function. In the later patch of this series, we will set the HCR_EL2.RW
for each vCPU while the domain is creating.
Signed-off-by: wei chen <wei.c...@arm.com>
, this may change in the
future. So we introduce this initcall to guarantee the cpu_hwcaps can be
updated no matter the serror parameter is placed in the command line
or not.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Acked-by: Julien Grall <julien.gr...@arm.com>
Reviewed-by: Stefan
.
The ARM64 supports the alternative patching feature. We can use an
ALTERNATIVE to avoid checking option at every trap. We added a new
cpufeature named "SKIP_CHECK_PENDING_VSERROR". This feature will be
enabled when the option is not diverse.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Revi
We have introduced two helpers to handle the guest/hyp SErrors:
do_trap_guest_serror and do_trap_guest_hyp_serror. These handlers
can take the role of do_trap_guest_serror and reduce the assembly
code in the same time. So we use these two helpers to replace it
and drop it now.
Signed-off-by: Wei
abort_guest_exit_start
and abort_guest_exit_end. After we move this macro to a common header,
we need to make sure that the two symbols are visible to other source
files. Currently, they are declared .global in arm32/entry.S, but not
arm64/entry.S. Fix that.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Re
#if 0 to disable it in this patch temporarily to remove the
warning message of unused function from compiler.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Acked-by: Stefano Stabellini <sstabell...@kernel.org>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
v2->
macro to synchronize SErrors while
returning to guest and doing context switch.
We also added a barrier to this macro to prevent compiler reorder our
asm volatile code.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v2->v3:
1. Use a macro to replace function to synchronize SErrors.
2.
, that would be a bug.
In the new helpers, we have used the function "inject_vabt_exception"
which was disabled by "#if 0" before. Now, we can remove the "#if 0"
to make this function to be available.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefan
ll avoid all
overhead of the dsb/isb pairs.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
v2->v3:
1. Replace "entries" to "entries and exits" in commit message and doc.
because all options will take effec
to avoid receiving nested asynchronous abort, we don't
unmask Abort/SError bit in hyp_error and trap_data_abort.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
---
xen/arch/arm/arm32/entry.S | 15 ++-
xen/arch/arm/arm64/
to disable the Abort/SError before returning to guest as we have done
for IRQ.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v2->v3:
1. Use alternative instead of check serror_op to skip sychronizing SErrors
while option is NOT "DIVERSE".
2. Disable Abort/SError before return
.
The ARM32 supports the alternative patching feature. We can use an
ALTERNATIVE to avoid checking option at every trap. We added a new
cpufeature named "SKIP_CHECK_PENDING_VSERROR". This feature will be
enabled when the option is not diverse.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Rev
The guest generated external data/instruction aborts can be treated
as guest SErrors. We already have a handler to handle the SErrors,
so we can reuse this handler to handle guest external aborts.
Signed-off-by: Wei Chen <wei.c...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@k
SErrors is pointless.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
xen/include/asm-arm/arm32/system.h | 7 +++
xen/include/asm-arm/arm64/system.h | 7 +++
2 files changed, 14 insertions(+)
diff --git a/xen/include/asm-arm/arm32/system.h
b/xen/include/asm-arm/arm32/system.h
index c
es.
Because we have umasked the Abort/SError bit in previous patch, we have
to disable Abort/SError before doing context switch as we have done for
IRQ.
Signed-off-by: Wei Chen <wei.c...@arm.com>
---
v2->v3:
1. Use the macro instead of the function to synchronize SErrors.
2. Disable Abor
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