ACPI/IORT Support in Xen.
--
Draft 3
Revision History:
Changes since v2:
- Modified as per comments from Julien /Sameer/Andre
Changes since v1:
- Modified IORT Parsing data structures.
- Added RID-StreamID and RID-DeviceID map as per Andre's suggestion.
On 11/16/2017 5:23 PM, Julien Grall wrote:
Hi Manish,
On 16/11/17 11:46, Manish Jaggi wrote:
On 11/16/2017 5:07 PM, Julien Grall wrote:
On 16/11/17 07:39, Manish Jaggi wrote:
On 11/14/2017 6:53 PM, Julien Grall wrote:
3. IORT for Dom0
-
IORT for Dom0 is based on host
On 11/16/2017 5:07 PM, Julien Grall wrote:
On 16/11/17 07:39, Manish Jaggi wrote:
On 11/14/2017 6:53 PM, Julien Grall wrote:
3. IORT for Dom0
-
IORT for Dom0 is based on host iort. Few nodes could be removed or
modified.
For instance
- Host SMMU nodes should
On 11/14/2017 6:53 PM, Julien Grall wrote:
Hi Manish,
Hey Julien,
On 08/11/17 14:38, Manish Jaggi wrote:
ACPI/IORT Support in Xen.
--
Draft 2
Revision History:
Changes since v1-
- Modified IORT Parsing data structures.
- Added RID->StreamID and RID->De
Hi Sameer
On 9/21/2017 6:07 AM, Sameer Goel wrote:
Add support for parsing IORT table to initialize SMMU devices.
* The code for creating an SMMU device has been modified, so that the SMMU
device can be initialized.
* The NAMED NODE code has been commented out as this will need DOM0 kernel
ACPI/IORT Support in Xen.
--
Draft 2
Revision History:
Changes since v1-
- Modified IORT Parsing data structures.
- Added RID->StreamID and RID->DeviceID map as per Andre's suggestion.
- Added reference code which can be read along with this document.
- Removed
On 10/31/2017 5:03 AM, Goel, Sameer wrote:
On 10/12/2017 3:03 PM, Manish Jaggi wrote:
ACPI/IORT Support in Xen.
--
I had sent out patch series [0] to hide smmu from Dom0 IORT. Extending the scope
and including all that is required to support ACPI/IORT
On 10/27/2017 7:35 PM, Andre Przywara wrote:
Hi,
Hey Andre,
On 25/10/17 09:22, Manish Jaggi wrote:
On 10/23/2017 7:27 PM, Andre Przywara wrote:
Hi Manish,
On 12/10/17 22:03, Manish Jaggi wrote:
ACPI/IORT Support in Xen.
--
I had sent out patch
On 10/23/2017 8:26 PM, Julien Grall wrote:
Hi,
On 23/10/17 14:57, Andre Przywara wrote:
On 12/10/17 22:03, Manish Jaggi wrote:
It is proposed that the idrange of PCIRC and ITS group be constant for
domUs.
"constant" is a bit confusing here. Maybe "arbitrary&
On 10/23/2017 7:27 PM, Andre Przywara wrote:
Hi Manish,
On 12/10/17 22:03, Manish Jaggi wrote:
ACPI/IORT Support in Xen.
--
I had sent out patch series [0] to hide smmu from Dom0 IORT. Extending
the scope
and including all that is required to support ACPI
On 10/19/2017 8:30 PM, Goel, Sameer wrote:
On 10/10/2017 6:36 AM, Manish Jaggi wrote:
Hi Sameer,
On 9/21/2017 6:07 AM, Sameer Goel wrote:
Add support for parsing IORT table to initialize SMMU devices.
* The code for creating an SMMU device has been modified, so that the SMMU
device can
On 10/12/2017 5:14 PM, Julien Grall wrote:
On 12/10/17 12:22, Manish Jaggi wrote:
Hi Julien,
Why do you omit parts of mail where I have asked a question , please
avoid skiping that removes the context.
I believe I answered it just after because you asked twice the same
thing. So may I
ACPI/IORT Support in Xen.
--
I had sent out patch series [0] to hide smmu from Dom0 IORT. Extending
the scope
and including all that is required to support ACPI/IORT in Xen.
Presenting for review
first _draft_ of design of ACPI/IORT support in Xen. Not
Please provide a technical answer rather than a simple "Why".
Cheers!
Manish
On 10/12/2017 4:34 PM, Julien Grall wrote:
Hello,
On 12/10/17 07:11, Manish Jaggi wrote:
On 10/6/2017 7:54 PM, Julien Grall wrote:
I am not asking to write the DomU support, but at least have a full
separatio
On 10/6/2017 7:54 PM, Julien Grall wrote:
Hello,
On 04/10/17 06:22, Manish Jaggi wrote:
On 10/4/2017 12:12 AM, Julien Grall wrote:
On 25/09/17 05:22, Manish Jaggi wrote:
On 9/22/2017 7:42 PM, Andre Przywara wrote:
Hi Manish,
On 11/09/17 22:33, mja...@caviumnetworks.com wrote:
From
Hi Julien,
On 10/10/2017 7:09 PM, Julien Grall wrote:
Hi Manish,
On 10/10/17 13:52, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
This patch extends the gicv3_iomem_deny_access functionality by adding
support for ITS region as well. Add fu
Hi Sameer,
On 9/21/2017 6:07 AM, Sameer Goel wrote:
Add support for parsing IORT table to initialize SMMU devices.
* The code for creating an SMMU device has been modified, so that the SMMU
device can be initialized.
* The NAMED NODE code has been commented out as this will need DOM0 kernel
On 10/10/2017 3:44 PM, Julien Grall wrote:
Hi Manish,
On 10/10/17 07:16, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
estimate_acpi_efi_size needs to be updated to provide correct size of
hardware domains MADT, which now adds ITS information as well.
This
Hi Andre,
On 10/3/2017 8:03 PM, Julien Grall wrote:
Hi Manish,
On 21/09/17 14:17, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
Add gicv3_its_make_hwdom_madt to update hwdom MADT ITS information.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
Hi
On 10/3/2017 8:01 PM, Julien Grall wrote:
Hi,
On 21/09/17 14:17, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
estimate_acpi_efi_size needs to be updated to provide correct size of
hardware domains MADT, which now adds ITS information as well.
Intro
Hello Julien,
On 10/3/2017 7:17 PM, Julien Grall wrote:
Hi Manish,
On 21/09/17 14:17, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
Added gicv3_its_acpi_init to update host_its_list from MADT table.
For ACPI, host_its structure stores dt_node as NULL.
Sign
Hello Julien,
On 10/4/2017 12:12 AM, Julien Grall wrote:
Hello,
On 25/09/17 05:22, Manish Jaggi wrote:
On 9/22/2017 7:42 PM, Andre Przywara wrote:
Hi Manish,
On 11/09/17 22:33, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
The set is divided into two p
Hi Andre,
On 9/22/2017 7:42 PM, Andre Przywara wrote:
Hi Manish,
On 11/09/17 22:33, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
The set is divided into two patches. First one calculates the size of IORT
while second one writes the IORT table itself.
It
Hi Sameer,
On 9/21/2017 6:07 AM, Sameer Goel wrote:
This change incoporates most of the review comments from [1] and adds the
proposed SMMUv3 driver.
List of changes:
- Introduce the iommu_fwspec implementation - No change from the last RFC
- IORT port from linux. The differences are as under:
On 9/7/2017 10:27 PM, Andre Przywara wrote:
Hi,
On 05/09/17 18:14, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@cavium.com>
This patch extends the gicv3_iomem_deny_access functionality by adding
support for ITS region as well. Add function gicv3_its_deny_access.
Sign
Hi All,
On 8/25/2017 4:12 PM, Julien Grall wrote:
Hi all,
I would suggest to have the next community call on Wednesday 13th
September 2017 5pm BST. Does it sound good?
Do you have any specific topic you would like to discuss?
Will it be possible to have a small discussion on the PCI
On 8/10/2017 6:44 PM, Julien Grall wrote:
On 08/10/2017 02:00 PM, Manish Jaggi wrote:
HI Julien,
On 8/10/2017 5:43 PM, Julien Grall wrote:
On 10/08/17 13:00, Manish Jaggi wrote:
Hi Julien,
On 8/10/2017 4:58 PM, Julien Grall wrote:
On 10/08/17 12:21, Manish Jaggi wrote:
Hi Julien
HI Julien,
On 8/10/2017 5:43 PM, Julien Grall wrote:
On 10/08/17 13:00, Manish Jaggi wrote:
Hi Julien,
On 8/10/2017 4:58 PM, Julien Grall wrote:
On 10/08/17 12:21, Manish Jaggi wrote:
Hi Julien,
On 6/21/2017 6:53 PM, Julien Grall wrote:
Hi Manish,
On 21/06/17 02:01, Manish Jaggi
Hi Julien,
On 8/10/2017 4:58 PM, Julien Grall wrote:
On 10/08/17 12:21, Manish Jaggi wrote:
Hi Julien,
On 6/21/2017 6:53 PM, Julien Grall wrote:
Hi Manish,
On 21/06/17 02:01, Manish Jaggi wrote:
This patch series adds the support of ITS for ACPI hardware domain.
It is tested on staging
Hi Julien,
On 6/21/2017 6:53 PM, Julien Grall wrote:
Hi Manish,
On 21/06/17 02:01, Manish Jaggi wrote:
This patch series adds the support of ITS for ACPI hardware domain.
It is tested on staging branch with has ITS v12 patchset by Andre.
I have tried to incorporate the review comments
On 6/13/2017 10:19 AM, Manish Jaggi wrote:
On 3/29/2017 5:30 AM, Goel, Sameer wrote:
Sure, I will try to post something soon.
Hi Sameer,
Are you still working on SMMU v3, can you please post patches.
Hi Sameer,
Could you please post RFC patches for SMMUv3, can provide feedback
Hi Julien,
On Mon, Jul 17, 2017 at 02:26:22PM +0100, Julien Grall wrote:
This email only tracks big items for xen.git tree. Please reply for items you
woulk like to see in 4.10 so that people have an idea what is going on and
prioritise accordingly.
You're welcome to provide description and
Hi Roger,
On 7/20/2017 3:59 PM, Roger Pau Monné wrote:
On Thu, Jul 20, 2017 at 03:02:19PM +0530, Manish Jaggi wrote:
Hi Roger,
On 7/20/2017 1:54 PM, Roger Pau Monné wrote:
On Thu, Jul 20, 2017 at 09:24:36AM +0530, Manish Jaggi wrote:
Hi Punit,
On 7/19/2017 8:11 PM, Punit Agrawal wrote:
I
HI Julien,
On 7/20/2017 4:11 PM, Julien Grall wrote:
On 20/07/17 10:32, Manish Jaggi wrote:
Hi Roger,
On 7/20/2017 1:54 PM, Roger Pau Monné wrote:
On Thu, Jul 20, 2017 at 09:24:36AM +0530, Manish Jaggi wrote:
Hi Punit,
On 7/19/2017 8:11 PM, Punit Agrawal wrote:
I took some notes
Hi Roger,
On 7/20/2017 1:54 PM, Roger Pau Monné wrote:
On Thu, Jul 20, 2017 at 09:24:36AM +0530, Manish Jaggi wrote:
Hi Punit,
On 7/19/2017 8:11 PM, Punit Agrawal wrote:
I took some notes for the PCI Passthrough design discussion at Xen
Summit. Due to the wide range of topics covered
Hi Punit,
On 7/19/2017 8:11 PM, Punit Agrawal wrote:
I took some notes for the PCI Passthrough design discussion at Xen
Summit. Due to the wide range of topics covered, the notes got sparser
towards the end of the session. I've tried to attribute names against
comments but have very likely got
This patch adds cavium,smmu-v2 compatible match entry in smmu driver
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/drivers/passthrough/arm/smmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/drivers/passthrough/arm/smmu.c
b/xen/drivers/passthrough/arm/smmu.c
index 1
This patch extends the gicv3_iomem_deny_access functionality by adding support
for its region as well. Added function gicv3_its_deny_access.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/gic-v3-its.c| 19 +++
xen/arch/arm/gic-v3.c
This patch adds ITS information in hardware domain's MADT table.
Also this patch interoduces .get_hwdom_madt_size in gic_hw_operations,
to return the complete size of MADT table for hardware domain.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/domain_build.c
in hardware domain's MADT table.
Also this patch interoduces .get_hwdom_madt_size in gic_hw_operations,
to return the complete size of MADT table for hardware domain.
Manish Jaggi (4):
ARM: ITS: Add translation_id to host_its
ARM: ITS: ACPI: Introduce gicv3_its_acpi_init
ARM: ITS: Deny
This patch adds gicv3_its_acpi_init. To avoid duplicate code for
initializing and adding to host_its_list a common function
add_to_host_its_list is added which is called by both _dt_init and _acpi_init.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/gic-v3-its.c
This patch adds a translation_id to host_its data structure.
Value stored in this id should be copied over to hardware domains
MADT table.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/include/asm-arm/gic_v3_its.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/inclu
Hi,
Does Xen arm64 support hugepages for Dom0 ? If yes how to enable it.
Found wiki page on it :
https://wiki.xenproject.org/wiki/Huge_Page_Support but is not updated.
Thanks
-Manish
___
Xen-devel mailing list
Xen-devel@lists.xen.org
This patch adds ITS information in hardware domain's MADT table.
Also this patch introduces .get_hwdom_madt_size in gic_hw_operations,
to return the complete size of MADT table for hardware domain.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/domain_build.c
This patch extends the gicv3_iomem_deny_access functionality by adding
support
for its region as well. Added function gicv3_its_deny_access.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/gic-v3-its.c| 19 +++
xen/arch/arm/gic-v3.c
This patch adds gicv3_its_acpi_init. To avoid duplicate code for
initializing and adding to host_its_list a common function
add_to_host_its_list is added which is called by both _dt_init and
_acpi_init.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/gic-v3-its.c
This patch adds a translation_id to host_its data structure.
Value stored in this id should be copied over to hardware domains
MADT table.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/include/asm-arm/gic_v3_its.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/inclu
information in hardware domain's MADT table.
Also this patch introduces .get_hwdom_madt_size in gic_hw_operations,
to return the complete size of MADT table for hardware domain.
Manish Jaggi (4):
ARM: ITS: Add translation_id to host_its
ARM: ITS: ACPI: Introduce gicv3_its_acpi_init
ARM: ITS: Deny
On 6/13/2017 4:58 PM, Julien Grall wrote:
On 13/06/17 12:02, Manish Jaggi wrote:
Will the below code be ok?
If you noticed, I didn't say this code is wrong. Instead I asked why
you use the same ID. Meaning, is there anything in the DSDT requiring
this value?
+ int tras_id = 0;
unsigned
Hi julien,
On 6/9/2017 2:09 PM, Julien Grall wrote:
On 09/06/2017 07:48, Manish Jaggi wrote:
On 6/8/2017 7:28 PM, Julien Grall wrote:
Hi,
Hello Julien,
Hello,
+list_for_each_entry(its_data, _its_list, entry)
+{
Pointless {
+size += sizeof(struct
On 3/29/2017 5:30 AM, Goel, Sameer wrote:
Sure, I will try to post something soon.
Hi Sameer,
Are you still working on SMMU v3, can you please post patches.
Thanks
Manish
Thanks,
Sameer
On 3/27/2017 11:03 PM, Vijay Kilari wrote:
On Mon, Mar 27, 2017 at 10:00 PM, Goel, Sameer
On 6/9/2017 11:11 PM, Andre Przywara wrote:
Hi,
Hi Andre,
Tested this patchset + my acpi ITS patch
(https://lists.xen.org/archives/html/xen-devel/2017-06/msg00716.html) on
our platform and it works.
With v10 was not able to get interrupts. v9 was booting ok.
WBR
-Manish
fixes to v10,
HI Julien,
On 6/9/2017 2:53 PM, Julien Grall wrote:
On 09/06/2017 08:13, Manish Jaggi wrote:
On 6/8/2017 6:39 PM, Julien Grall wrote:
Hi Manish,
Hi Julien,
Hello,
On 08/06/17 13:38, Manish Jaggi wrote:
Spurious line.
This patch disables the smmu node in IORT table for hardware
On 6/8/2017 6:39 PM, Julien Grall wrote:
Hi Manish,
Hi Julien,
On 08/06/17 13:38, Manish Jaggi wrote:
Spurious line.
This patch disables the smmu node in IORT table for hardware domain.
Also patches the output_base of pci_rc id_array with output_base of
smmu node id_array.
I would
On 6/8/2017 7:28 PM, Julien Grall wrote:
Hi,
Hello Julien,
Please CC all relevant maintainers.
Sure. Will do in the next patch rev.
On 08/06/17 14:03, Manish Jaggi wrote:
Spurious newline
This patch supports ITS in hardware domain, supports ITS in Xen
when booting with ACPI.
Signed
This patch supports ITS in hardware domain, supports ITS in Xen
when booting with ACPI.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
Changes since v1:
- Moved its specific code to gic-v3-its.c
- fixed macros
xen/arch/arm/domain_build.c | 6 ++--
xen/arch/arm/gic-v3
This patch disables the smmu node in IORT table for hardware domain.
Also patches the output_base of pci_rc id_array with output_base of
smmu node id_array.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/domain_build.c | 142
+++-
On 5/19/2017 1:39 AM, Julien Grall wrote:
On 18/05/2017 21:02, Manish Jaggi wrote:
In the IORT table using the PCI-RC node, SMMU node and ITS node,
RID->StreamID->Device-ID mapping can be generated.
As per IORT spec toady, same RID can be mapped to different StreamIDs
using two ID
This patch supports ITS in hardware domain, supports ITS in Xen when
booting with ACPI. Signed-off-by: Manish Jaggi <mja...@cavium.com> ---
Changes since v1: - Moved its specific code to gic-v3-its.c - fixed
macros xen/arch/arm/domain_build.c | 6 ++-- xen/arch/arm/gic-v3-its.c
Hi Julien,
On 5/30/2017 4:07 PM, Julien Grall wrote:
Hello Manish,
On 30/05/17 07:07, Manish Jaggi wrote:
This patch is an RFC on top of Andre's v10 series.
https://www.mail-archive.com/xen-devel@lists.xen.org/msg109093.html
This patch deny's access to ITS region for the guest and also
This patch is an RFC on top of Andre's v10 series.
https://www.mail-archive.com/xen-devel@lists.xen.org/msg109093.html
This patch deny's access to ITS region for the guest and also updates
the acpi tables for dom0.
Signed-off-by: Manish Jaggi <mja...@cavium.com>
---
xen/arch/arm/gi
Hi Julien,
On 5/29/2017 11:44 PM, Julien Grall wrote:
On 05/29/2017 03:30 AM, Manish Jaggi wrote:
Hi Julien,
Hello Manish,
On 5/26/2017 10:44 PM, Julien Grall wrote:
PCI pass-through allows the guest to receive full control of
physical PCI
devices. This means the guest will have full
Hi Julien,
On 5/26/2017 10:44 PM, Julien Grall wrote:
Hi all,
The document below is an RFC version of a design proposal for PCI
Passthrough in Xen on ARM. It aims to describe from an high level perspective
the interaction with the different subsystems and how guest will be able
to discover and
Hi Julien,
On 5/18/2017 8:27 PM, Julien Grall wrote:
Hello,
On 18/05/17 12:59, Manish Jaggi wrote:
On 2/27/2017 11:42 PM, Julien Grall wrote:
On 02/27/2017 04:58 PM, Shanker Donthineni wrote:
Hi Julien,
Hi Shanker,
Please don't drop people in CC. In my case, any e-mail I am not CCed
+Chales.
Hi Julien,
On 2/27/2017 11:42 PM, Julien Grall wrote:
On 02/27/2017 04:58 PM, Shanker Donthineni wrote:
Hi Julien,
Hi Shanker,
Please don't drop people in CC. In my case, any e-mail I am not CCed
are skipping my inbox and I may not read them for a while.
On 02/27/2017 08:12
Hello Julien,
On 01/25/2017 08:55 PM, Julien Grall wrote:
> Hello Manish,
>
> On 25/01/17 04:37, Manish Jaggi wrote:
>> On 01/24/2017 11:13 PM, Julien Grall wrote:
>>>
>>>
>>> On 19/01/17 05:09, Manish Jaggi wrote:
>>>> I think, PCI
On 01/24/2017 11:13 PM, Julien Grall wrote:
>
>
> On 19/01/17 05:09, Manish Jaggi wrote:
>> Hi Julien,
>
> Hello Manish,
[snip]
>> I think, PCI passthrough and DOM0 w/ACPI enumerating devices on PCI are
>> separate features.
>> Without Xen mapping PC
Hi Julien/Stefano,
On 01/24/2017 07:58 PM, Julien Grall wrote:
> Hi Stefano,
>
> On 04/01/17 00:24, Stefano Stabellini wrote:
>> On Thu, 29 Dec 2016, Julien Grall wrote:
>
> [...]
>
>>> # Introduction
>>>
>>> PCI passthrough allows to give control of physical PCI devices to guest.
>>> This
Hi Julien,
On 12/29/2016 07:34 PM, Julien Grall wrote:
> Hi all,
>
> The document below is an early version of a design
> proposal for PCI Passthrough in Xen. It aims to
> describe from an high level perspective the interaction
> with the different subsystems and how guest will be able
> to
-
| PCI Pass-through in Xen ARM |
-
manish.ja...@cavium.com
-
Draft-5
On Wednesday 16 September 2015 06:28 PM, Julien Grall wrote:
On 15/09/15 19:58, Jaggi, Manish wrote:
I can see 2 different solutions:
1) Let DOM0 pass the first requester ID when registering the bus
Pros:
* Less per-platform code in Xen
Cons:
* Assume
On Tuesday 01 September 2015 01:02 PM, Jan Beulich wrote:
On 31.08.15 at 14:36, <mja...@caviumnetworks.com> wrote:
On Thursday 13 August 2015 03:12 PM, Manish Jaggi wrote:
4.2.1 Mapping BAR regions in guest address
On Thursday 13 August 2015 03:12 PM, Manish Jaggi wrote:
-
| PCI Pass-through in Xen ARM |
-
manish.ja...@caviumnetworks.com
---
Draft
-
| PCI Pass-through in Xen ARM |
-
manish.ja...@caviumnetworks.com
---
Draft-4
Below are the comments. I will also send a Draft 4 taking account of the
comments.
On Wednesday 12 August 2015 02:04 AM, Konrad Rzeszutek Wilk wrote:
On Tue, Aug 04, 2015 at 05:57:24PM +0530, Manish Jaggi wrote:
-
| PCI Pass-through
-
| PCI Pass-through in Xen ARM |
-
manish.ja...@caviumnetworks.com
---
Draft-3
On 31/07/15 4:49 pm, Ian Campbell wrote:
On Fri, 2015-07-31 at 16:37 +0530, Manish Jaggi wrote:
On Friday 31 July 2015 01:35 PM, Ian Campbell wrote:
On Fri, 2015-07-31 at 13:16 +0530, Manish Jaggi wrote:
Secondly, the vdev-X entry is created async by dom0 watching on
event.
So how the tools
On 31/07/15 8:26 pm, Julien Grall wrote:
On 31/07/15 15:33, Manish Jaggi wrote:
Hi Julien,
On 31/07/15 6:29 pm, Julien Grall wrote:
Hi Manish,
On 31/07/15 13:50, Manish Jaggi wrote:
Ok, i will implement the same from pciback to toolstack. I am not sure
about the complexity but will give
Hi Julien,
On 31/07/15 6:29 pm, Julien Grall wrote:
Hi Manish,
On 31/07/15 13:50, Manish Jaggi wrote:
Ok, i will implement the same from pciback to toolstack. I am not sure
about the complexity but will give it a try.
With this xen-pciback will not create the vdev-X entry at all.
Can you
On Friday 31 July 2015 01:35 PM, Ian Campbell wrote:
On Fri, 2015-07-31 at 13:16 +0530, Manish Jaggi wrote:
Secondly, the vdev-X entry is created async by dom0 watching on
event.
So how the tools could read back and call assign device again.
Perhaps by using a xenstore watch on that node
On Thursday 30 July 2015 03:24 PM, Ian Campbell wrote:
On Wed, 2015-07-29 at 15:07 +0530, Manish Jaggi wrote:
On Monday 06 July 2015 03:50 PM, Ian Campbell wrote:
On Mon, 2015-07-06 at 15:36 +0530, Manish Jaggi wrote:
On Monday 06 July 2015 02:41 PM, Ian Campbell wrote:
On Sun, 2015-07-05
On Monday 06 July 2015 03:50 PM, Ian Campbell wrote:
On Mon, 2015-07-06 at 15:36 +0530, Manish Jaggi wrote:
On Monday 06 July 2015 02:41 PM, Ian Campbell wrote:
On Sun, 2015-07-05 at 11:25 +0530, Manish Jaggi wrote:
On Monday 29 June 2015 04:01 PM, Julien Grall wrote:
Hi Manish,
On 28/06
On Tuesday 14 July 2015 11:31 PM, Stefano Stabellini wrote:
On Tue, 14 Jul 2015, Julien Grall wrote:
Hi Stefano,
On 14/07/2015 18:46, Stefano Stabellini wrote:
Linux provides a function (pci_for_each_dma_alias) which will return a
requester ID for a given PCI device. It appears that the BDF
On Tuesday 07 July 2015 04:54 PM, Ian Campbell wrote:
On Tue, 2015-07-07 at 14:16 +0530, Manish Jaggi wrote:
As asked you in the previous mail, can you please prove it? The
function used to get the requester ID (pci_for_each_dma_alias) is more
complex than a simple return sbdf.
I am not sure
On Thursday 09 July 2015 01:38 PM, Julien Grall wrote:
Hi Manish,
On 09/07/2015 08:13, Manish Jaggi wrote:
If this was a domctl there might be scope for accepting an
implementation which made assumptions such as sbdf == deviceid. However
I'd still like to see this topic given proper
On Tuesday 07 July 2015 01:48 PM, Julien Grall wrote:
Hi Manish,
On 07/07/2015 08:10, Manish Jaggi wrote:
On Monday 06 July 2015 05:15 PM, Julien Grall wrote:
On 06/07/15 12:09, Manish Jaggi wrote:
On Monday 06 July 2015 04:13 PM, Julien Grall wrote:
On 05/07/15 06:55, Manish Jaggi wrote
On Monday 06 July 2015 05:15 PM, Julien Grall wrote:
On 06/07/15 12:09, Manish Jaggi wrote:
On Monday 06 July 2015 04:13 PM, Julien Grall wrote:
On 05/07/15 06:55, Manish Jaggi wrote:
4.3 Hypercall for bdf mapping notification to xen
---
#define
On Tuesday 07 July 2015 02:16 PM, Manish Jaggi wrote:
On Tuesday 07 July 2015 01:48 PM, Julien Grall wrote:
Hi Manish,
On 07/07/2015 08:10, Manish Jaggi wrote:
On Monday 06 July 2015 05:15 PM, Julien Grall wrote:
On 06/07/15 12:09, Manish Jaggi wrote:
On Monday 06 July 2015 04:13 PM
On Monday 06 July 2015 04:13 PM, Julien Grall wrote:
On 05/07/15 06:55, Manish Jaggi wrote:
4.3 Hypercall for bdf mapping notification to xen
---
#define PHYSDEVOP_map_sbdf 43
typedef struct {
u32 s;
u8 b;
u8 df
On Monday 06 July 2015 02:41 PM, Ian Campbell wrote:
On Sun, 2015-07-05 at 11:25 +0530, Manish Jaggi wrote:
On Monday 29 June 2015 04:01 PM, Julien Grall wrote:
Hi Manish,
On 28/06/15 19:38, Manish Jaggi wrote:
4.1 Holes in guest memory space
Holes are added
On Sunday 05 July 2015 11:25 AM, Manish Jaggi wrote:
On Monday 29 June 2015 04:01 PM, Julien Grall wrote:
Hi Manish,
On 28/06/15 19:38, Manish Jaggi wrote:
4.1 Holes in guest memory space
Holes are added in the guest memory space for mapping pci device's BAR
Ian Campbell Wrote:
On Mon, 2015-06-29 at 00:08 +0530, Manish Jaggi wrote:
PCI Pass-through in Xen ARM
--
Draft 2
Index
1. Background
2. Basic PCI Support in Xen ARM
2.1 pci_hostbridge and pci_hostbridge_ops
2.2 PHYSDEVOP_HOSTBRIDGE_ADD hypercall
3. Dom0 Access PCI
On Monday 29 June 2015 04:01 PM, Julien Grall wrote:
Hi Manish,
On 28/06/15 19:38, Manish Jaggi wrote:
4.1 Holes in guest memory space
Holes are added in the guest memory space for mapping pci device's BAR
regions.
These are defined in arch-arm.h
/* For 32bit
PCI Pass-through in Xen ARM
--
Draft 2
Index
1. Background
2. Basic PCI Support in Xen ARM
2.1 pci_hostbridge and pci_hostbridge_ops
2.2 PHYSDEVOP_HOSTBRIDGE_ADD hypercall
3. Dom0 Access PCI devices
4. DomU assignment of PCI device
4.1 Holes in guest memory space
4.2
On Friday 26 June 2015 01:02 PM, Ian Campbell wrote:
On Fri, 2015-06-26 at 07:37 +0530, Manish Jaggi wrote:
On Thursday 25 June 2015 10:56 PM, Konrad Rzeszutek Wilk wrote:
On Thu, Jun 25, 2015 at 01:21:28PM +0100, Ian Campbell wrote:
On Thu, 2015-06-25 at 17:29 +0530, Manish Jaggi wrote
On Friday 26 June 2015 02:39 PM, Ian Campbell wrote:
On Fri, 2015-06-26 at 14:20 +0530, Manish Jaggi wrote:
On Friday 26 June 2015 01:02 PM, Ian Campbell wrote:
On Fri, 2015-06-26 at 07:37 +0530, Manish Jaggi wrote:
On Thursday 25 June 2015 10:56 PM, Konrad Rzeszutek Wilk wrote:
On Thu
On Wednesday 17 June 2015 07:59 PM, Ian Campbell wrote:
On Wed, 2015-06-17 at 07:14 -0700, Manish Jaggi wrote:
On Wednesday 17 June 2015 06:43 AM, Ian Campbell wrote:
On Wed, 2015-06-17 at 13:58 +0100, Stefano Stabellini wrote:
Yes, pciback is already capable of doing that, see
drivers/xen
On Thursday 25 June 2015 02:41 PM, Ian Campbell wrote:
On Thu, 2015-06-25 at 13:14 +0530, Manish Jaggi wrote:
On Wednesday 17 June 2015 07:59 PM, Ian Campbell wrote:
On Wed, 2015-06-17 at 07:14 -0700, Manish Jaggi wrote:
On Wednesday 17 June 2015 06:43 AM, Ian Campbell wrote:
On Wed, 2015
On Thursday 25 June 2015 10:56 PM, Konrad Rzeszutek Wilk wrote:
On Thu, Jun 25, 2015 at 01:21:28PM +0100, Ian Campbell wrote:
On Thu, 2015-06-25 at 17:29 +0530, Manish Jaggi wrote:
On Thursday 25 June 2015 02:41 PM, Ian Campbell wrote:
On Thu, 2015-06-25 at 13:14 +0530, Manish Jaggi wrote
On Wednesday 17 June 2015 06:43 AM, Ian Campbell wrote:
On Wed, 2015-06-17 at 13:58 +0100, Stefano Stabellini wrote:
Yes, pciback is already capable of doing that, see
drivers/xen/xen-pciback/conf_space.c
I am not sure if the pci-back driver can query the guest memory map. Is there
an
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