Re: [Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

On 08/08/2016 10:09 AM, Jan Beulich wrote: >> The reserved bits look the same on all supported families --- bits >> 63:42, 39:36, 21 and 19. Except apparently on family 12h bit 19 is MBZ. > Isn't MBZ == reserved for all practical purposes? My understanding is that when something is MBZ we know

Re: [Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

>>> On 08.08.16 at 17:05, wrote: > On 08/08/2016 10:09 AM, Jan Beulich wrote: >>> The reserved bits look the same on all supported families --- bits >>> 63:42, 39:36, 21 and 19. Except apparently on family 12h bit 19 is MBZ. >> Isn't MBZ == reserved for all practical

Re: [Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

>>> On 08.08.16 at 16:06, wrote: > On 08/08/2016 09:53 AM, Jan Beulich wrote: > On 08.08.16 at 15:41, wrote: >>> --- a/xen/arch/x86/traps.c >>> +++ b/xen/arch/x86/traps.c >>> @@ -2903,6 +2903,7 @@ static int emulate_privileged_op(struct

Re: [Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

On 08/08/2016 09:53 AM, Jan Beulich wrote: On 08.08.16 at 15:41, wrote: >> --- a/xen/arch/x86/traps.c >> +++ b/xen/arch/x86/traps.c >> @@ -2903,6 +2903,7 @@ static int emulate_privileged_op(struct cpu_user_regs >> *regs) >> { >>

Re: [Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

>>> On 08.08.16 at 15:41, wrote: > --- a/xen/arch/x86/traps.c > +++ b/xen/arch/x86/traps.c > @@ -2903,6 +2903,7 @@ static int emulate_privileged_op(struct cpu_user_regs > *regs) > { > vpmu_msr = 1; > case

[Xen-devel] [PATCH 1/2] AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range

We need to check for older PMU MSR range when emulating MSR accesses for PV guests. Signed-off-by: Boris Ostrovsky --- xen/arch/x86/traps.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 767d0b0..79a3516 100644